snapshot: sagernet/gvisor v0.0.0-20260727.0-sing-box-mod.1 + SPEC 048 guard
Обновление снапшота с v0.0.0-20250811.0 на пин, которого требует sing-box после мержа 235 коммитов (upstream d620bbbf2 "Update gvisor to 20260727.0"). Прежний снапшот был взят 2026-08-04 ровно с той версии, на которой тогда стоял апстрим; разрыв возник 2026-08-05 вместе с его бампом. За год апстрим-gvisor изменил ~14 000 строк в 292 файлах. Значимое для нас — сетевой стек: tcp/connect.go (PMTU-discovery + исправление начального RTT/RTO: раньше задержка ACK внутри стека завышала стартовый таймаут на несколько RTT), tcp/snd.go, tcp/rcv.go, stack/conntrack.go, stack/packet_buffer.go. Всего 30 файлов в TCP и 37 в stack. Баг SPEC 048 апстрим НЕ исправил — проверено по коду новой версии: handleConnecting по-прежнему проверяет состояние endpoint'а, но не ep.h, а performHandshake так же зануляет h и отпускает мьютекс до Close(). Поэтому guard перенесён (12 строк) вместе со своим тестом (45 строк). Red/green проверен на новой базе: без guard'а тест падает с той же nil-паникой, что в полевом крашдампе; с ним зелёный.
This commit is contained in:
Leadaxe
parent
ffebe42860
commit
117243aa02
293 changed files with 16413 additions and 2842 deletions
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@ -16,6 +16,7 @@ package nvgpu
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import (
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"fmt"
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"structs"
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)
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// ClassID is a client class ID, in the sense of
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@ -58,7 +59,10 @@ const (
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NV01_DEVICE_0 = 0x00000080
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NV_SEMAPHORE_SURFACE = 0x000000da
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RM_USER_SHARED_DATA = 0x000000de
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NV_MEMORY_EXPORT = 0x000000e0
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NV_IMEX_SESSION = 0x000000f1
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NV_MEMORY_FABRIC = 0x000000f8
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NV_MEMORY_FABRIC_IMPORTED_REF = 0x000000fb
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NV_MEMORY_MULTICAST_FABRIC = 0x000000fd
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NV_MEMORY_MAPPER = 0x000000fe
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NV20_SUBDEVICE_0 = 0x00002080
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@ -67,56 +71,72 @@ const (
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NV50_THIRD_PARTY_P2P = 0x0000503c
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NV50_MEMORY_VIRTUAL = 0x000050a0
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GT200_DEBUGGER = 0x000083de
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MPS_COMPUTE = 0x0000900e
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FERMI_TWOD_A = 0x0000902d
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FERMI_CONTEXT_SHARE_A = 0x00009067
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GF100_DISP_SW = 0x00009072
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GF100_ZBC_CLEAR = 0x00009096
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GF100_SUBDEVICE_INFOROM = 0x000090e7
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GF100_PROFILER = 0x000090cc
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MAXWELL_PROFILER_DEVICE = 0x0000b2cc
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NV_COUNTER_COLLECTION_UNIT = 0x0000cbca
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GF100_SUBDEVICE_MASTER = 0x000090e6
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FERMI_VASPACE_A = 0x000090f1
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KEPLER_CHANNEL_GROUP_A = 0x0000a06c
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NVENC_SW_SESSION = 0x0000a0bc
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KEPLER_INLINE_TO_MEMORY_B = 0x0000a140
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NVB8B0_VIDEO_DECODER = 0x0000b8b0
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NVB8D1_VIDEO_NVJPG = 0x0000b8d1
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NVB8FA_VIDEO_OFA = 0x0000b8fa
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VOLTA_USERMODE_A = 0x0000c361
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TURING_USERMODE_A = 0x0000c461
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TURING_CHANNEL_GPFIFO_A = 0x0000c46f
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NVB8B0_VIDEO_DECODER = 0x0000b8b0 // Hopper
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NVC4B0_VIDEO_DECODER = 0x0000c4b0 // Turing
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NVC6B0_VIDEO_DECODER = 0x0000c6b0 // Ampere
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NVC7B0_VIDEO_DECODER = 0x0000c7b0 // Ampere
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NVC9B0_VIDEO_DECODER = 0x0000c9b0 // Ada
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NVCDB0_VIDEO_DECODER = 0x0000cdb0 // Blackwell
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NVC4B0_VIDEO_DECODER = 0x0000c4b0
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NVC4B7_VIDEO_ENCODER = 0x0000c4b7
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NVC7B7_VIDEO_ENCODER = 0x0000c7b7
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NVC9B7_VIDEO_ENCODER = 0x0000c9b7
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NVC4D1_VIDEO_NVJPG = 0x0000c4d1
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AMPERE_CHANNEL_GPFIFO_A = 0x0000c56f
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TURING_A = 0x0000c597
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TURING_DMA_COPY_A = 0x0000c5b5
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TURING_COMPUTE_A = 0x0000c5c0
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HOPPER_USERMODE_A = 0x0000c661
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BLACKWELL_USERMODE_A = 0x0000c761
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AMPERE_A = 0x0000c697
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NVC6B0_VIDEO_DECODER = 0x0000c6b0
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AMPERE_DMA_COPY_A = 0x0000c6b5
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AMPERE_COMPUTE_A = 0x0000c6c0
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NVC6FA_VIDEO_OFA = 0x0000c6fa
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BLACKWELL_USERMODE_A = 0x0000c761
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NVC7B0_VIDEO_DECODER = 0x0000c7b0
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AMPERE_DMA_COPY_B = 0x0000c7b5
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NVC7B7_VIDEO_ENCODER = 0x0000c7b7
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AMPERE_COMPUTE_B = 0x0000c7c0
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NVC7FA_VIDEO_OFA = 0x0000c7fa
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HOPPER_CHANNEL_GPFIFO_A = 0x0000c86f
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HOPPER_DMA_COPY_A = 0x0000c8b5
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BLACKWELL_CHANNEL_GPFIFO_A = 0x0000c96f
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ADA_A = 0x0000c997
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NVC9B0_VIDEO_DECODER = 0x0000c9b0
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BLACKWELL_DMA_COPY_A = 0x0000c9b5
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NVC9B7_VIDEO_ENCODER = 0x0000c9b7
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ADA_COMPUTE_A = 0x0000c9c0
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NVC9D1_VIDEO_NVJPG = 0x0000c9d1
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NVC9FA_VIDEO_OFA = 0x0000c9fa
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BLACKWELL_CHANNEL_GPFIFO_B = 0x0000ca6f
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BLACKWELL_DMA_COPY_B = 0x0000cab5
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ADA_A = 0x0000c997
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ADA_COMPUTE_A = 0x0000c9c0
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NV_CONFIDENTIAL_COMPUTE = 0x0000cb33
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HOPPER_A = 0x0000cb97
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HOPPER_SEC2_WORK_LAUNCH_A = 0x0000cba2
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HOPPER_COMPUTE_A = 0x0000cbc0
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BLACKWELL_INLINE_TO_MEMORY_A = 0x0000cd40
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BLACKWELL_A = 0x0000cd97
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NVCDB0_VIDEO_DECODER = 0x0000cdb0
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BLACKWELL_COMPUTE_A = 0x0000cdc0
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NVCDD1_VIDEO_NVJPG = 0x0000cdd1
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NVCDFA_VIDEO_OFA = 0x0000cdfa
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BLACKWELL_B = 0x0000ce97
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NVCEB7_VIDEO_ENCODER = 0x0000ceb7
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BLACKWELL_COMPUTE_B = 0x0000cec0
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NVCFB7_VIDEO_ENCODER = 0x0000cfb7
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NVD1B7_VIDEO_ENCODER = 0x0000d1b7
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)
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// From src/common/sdk/nvidia/inc/class/cl0000.h:
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@ -129,6 +149,7 @@ const (
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//
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// +marshal
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type NV2081_ALLOC_PARAMETERS struct {
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_ structs.HostLayout
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Reserved uint32
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}
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@ -137,6 +158,7 @@ type NV2081_ALLOC_PARAMETERS struct {
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//
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// +marshal
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type NV0005_ALLOC_PARAMETERS struct {
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_ structs.HostLayout
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HParentClient Handle
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HSrcResource Handle
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HClass ClassID
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@ -159,6 +181,7 @@ const (
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//
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// +marshal
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type NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS struct {
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_ structs.HostLayout
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Offset uint64
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Limit uint64
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HVASpace Handle
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@ -175,6 +198,7 @@ const (
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//
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// +marshal
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type NV0080_ALLOC_PARAMETERS struct {
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_ structs.HostLayout
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DeviceID uint32
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HClientShare Handle
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HTargetClient Handle
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@ -193,6 +217,7 @@ type NV0080_ALLOC_PARAMETERS struct {
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//
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// +marshal
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type NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS struct {
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_ structs.HostLayout
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HSemaphoreMem Handle
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HMaxSubmittedMem Handle
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flags uint64
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@ -203,6 +228,7 @@ type NV_SEMAPHORE_SURFACE_ALLOC_PARAMETERS struct {
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//
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// +marshal
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type NV2080_ALLOC_PARAMETERS struct {
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_ structs.HostLayout
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SubDeviceID uint32
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}
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@ -211,6 +237,7 @@ type NV2080_ALLOC_PARAMETERS struct {
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//
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// +marshal
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type NV_CONTEXT_DMA_ALLOCATION_PARAMS struct {
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_ structs.HostLayout
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HSubDevice Handle
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Flags uint32
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HMemory Handle
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@ -224,6 +251,7 @@ type NV_CONTEXT_DMA_ALLOCATION_PARAMS struct {
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//
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// +marshal
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type NV_MEMORY_ALLOCATION_PARAMS struct {
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_ structs.HostLayout
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Owner uint32
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Type uint32
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Flags uint32
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@ -254,6 +282,7 @@ type NV_MEMORY_ALLOCATION_PARAMS struct {
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//
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// +marshal
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type NV_MEMORY_ALLOCATION_PARAMS_V545 struct {
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_ structs.HostLayout
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NV_MEMORY_ALLOCATION_PARAMS
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NumaNode int32
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_ uint32
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@ -263,6 +292,7 @@ type NV_MEMORY_ALLOCATION_PARAMS_V545 struct {
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//
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// +marshal
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type NV503B_BAR1_P2P_DMA_INFO struct {
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_ structs.HostLayout
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DmaAddress uint64
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DmaSize uint64
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}
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@ -272,6 +302,7 @@ type NV503B_BAR1_P2P_DMA_INFO struct {
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//
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// +marshal
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type NV503B_ALLOC_PARAMETERS struct {
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_ structs.HostLayout
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HSubDevice Handle
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HPeerSubDevice Handle
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SubDevicePeerIDMask uint32
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@ -285,11 +316,31 @@ type NV503B_ALLOC_PARAMETERS struct {
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P2lBar1P2PDmaInfo NV503B_BAR1_P2P_DMA_INFO
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}
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// NV503B_FABRIC_P2P_DMA_INFO from src/common/sdk/nvidia/inc/class/cl503b.h.
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//
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// +marshal
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type NV503B_FABRIC_P2P_DMA_INFO struct {
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_ structs.HostLayout
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Gpa uint64
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}
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// NV503B_ALLOC_PARAMETERS_V590 is the updated version of
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// NV503B_ALLOC_PARAMETERS since 590.44.01.
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//
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// +marshal
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type NV503B_ALLOC_PARAMETERS_V590 struct {
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_ structs.HostLayout
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NV503B_ALLOC_PARAMETERS
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L2pFabricP2PInfo NV503B_FABRIC_P2P_DMA_INFO
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P2lFabricP2PInfo NV503B_FABRIC_P2P_DMA_INFO
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}
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// NV503C_ALLOC_PARAMETERS is the alloc params type for NV50_THIRD_PARTY_P2P,
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// from src/common/sdk/nvidia/inc/class/cl503c.h.
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//
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// +marshal
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type NV503C_ALLOC_PARAMETERS struct {
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_ structs.HostLayout
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Flags uint32
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}
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@ -298,6 +349,7 @@ type NV503C_ALLOC_PARAMETERS struct {
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//
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// +marshal
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type NV83DE_ALLOC_PARAMETERS struct {
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_ structs.HostLayout
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HDebuggerClient_Obsolete Handle
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HAppClient Handle
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HClass3DObject Handle
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@ -308,6 +360,7 @@ type NV83DE_ALLOC_PARAMETERS struct {
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//
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// +marshal
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type NV_CTXSHARE_ALLOCATION_PARAMETERS struct {
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_ structs.HostLayout
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HVASpace Handle
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Flags uint32
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SubctxID uint32
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@ -318,6 +371,7 @@ type NV_CTXSHARE_ALLOCATION_PARAMETERS struct {
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//
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// +marshal
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type NV_VASPACE_ALLOCATION_PARAMETERS struct {
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_ structs.HostLayout
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Index uint32
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Flags uint32
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VASize uint64
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@ -333,6 +387,7 @@ type NV_VASPACE_ALLOCATION_PARAMETERS struct {
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//
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// +marshal
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type NV_VASPACE_ALLOCATION_PARAMETERS_V580 struct {
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_ structs.HostLayout
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NV_VASPACE_ALLOCATION_PARAMETERS
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Pasid uint32
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Pad1 [4]byte
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@ -343,6 +398,7 @@ type NV_VASPACE_ALLOCATION_PARAMETERS_V580 struct {
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//
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// +marshal
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type NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS struct {
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_ structs.HostLayout
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HObjectError Handle
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HObjectECCError Handle
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HVASpace Handle
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@ -356,6 +412,7 @@ type NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS struct {
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//
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// +marshal
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type NV_MEMORY_DESC_PARAMS struct {
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_ structs.HostLayout
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Base uint64
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Size uint64
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AddressSpace uint32
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@ -365,8 +422,12 @@ type NV_MEMORY_DESC_PARAMS struct {
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// NV_BSP_ALLOCATION_PARAMETERS is the alloc params type for
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// NV*VIDEO_DECODER, from src/common/sdk/nvidia/inc/nvos.h.
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//
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// It is also used to represent the following driver structs:
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// - NV_NVDEC_ALLOCATION_PARAMETERS
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//
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// +marshal
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type NV_BSP_ALLOCATION_PARAMETERS struct {
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_ structs.HostLayout
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Size uint32
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ProhibitMultipleInstances uint32
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EngineInstance uint32
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@ -375,8 +436,12 @@ type NV_BSP_ALLOCATION_PARAMETERS struct {
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// NV_MSENC_ALLOCATION_PARAMETERS is the alloc params type for
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// NV*_VIDEO_ENCODER, from src/common/sdk/nvidia/inc/nvos.h.
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//
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// It is also used to represent the following driver structs:
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// - NV_NVENC_ALLOCATION_PARAMETERS
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//
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// +marshal
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type NV_MSENC_ALLOCATION_PARAMETERS struct {
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_ structs.HostLayout
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Size uint32
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ProhibitMultipleInstances uint32
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EngineInstance uint32
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@ -388,6 +453,7 @@ type NV_MSENC_ALLOCATION_PARAMETERS struct {
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//
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// +marshal
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type NV_CHANNEL_ALLOC_PARAMS struct {
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_ structs.HostLayout
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HObjectError Handle
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HObjectBuffer Handle
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GPFIFOOffset uint64
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@ -421,17 +487,57 @@ type NV_CHANNEL_ALLOC_PARAMS struct {
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//
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// +marshal
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type NV_CHANNEL_ALLOC_PARAMS_V570 struct {
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_ structs.HostLayout
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NV_CHANNEL_ALLOC_PARAMS
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TPCConfigID uint32
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_ uint32
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}
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// NV_CHANNEL_ALLOC_PARAMS_V610 is the updated version of
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// NV_CHANNEL_ALLOC_PARAMS since 610.43.02.
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//
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// +marshal
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type NV_CHANNEL_ALLOC_PARAMS_V610 struct {
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_ structs.HostLayout
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HObjectError Handle
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HObjectBuffer Handle
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GPFIFOOffset uint64
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GPFIFOEntries uint32
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Flags uint32
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HContextShare Handle
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HVASpace Handle
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HHandleVASpace Handle
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HUserdMemory [NV_MAX_SUBDEVICES]Handle
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_ uint32
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UserdOffset [NV_MAX_SUBDEVICES]uint64
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EngineType uint32
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CID uint32
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SubDeviceID uint32
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HObjectECCError Handle
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InstanceMem NV_MEMORY_DESC_PARAMS
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UserdMem NV_MEMORY_DESC_PARAMS
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RamfcMem NV_MEMORY_DESC_PARAMS
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MthdbufMem NV_MEMORY_DESC_PARAMS
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HPhysChannelGroup Handle
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InternalFlags uint32
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ErrorNotifierMem NV_MEMORY_DESC_PARAMS
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ECCErrorNotifierMem NV_MEMORY_DESC_PARAMS
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ProcessID uint32
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SubProcessID uint32
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EncryptIv [CC_CHAN_ALLOC_IV_SIZE_DWORD]uint32
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DecryptIv [CC_CHAN_ALLOC_IV_SIZE_DWORD]uint32
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HmacNonce [CC_CHAN_ALLOC_NONCE_SIZE_DWORD]uint32
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TPCConfigID uint32
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_ uint32
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}
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// NVB0B5_ALLOCATION_PARAMETERS is the alloc param type for TURING_DMA_COPY_A,
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// AMPERE_DMA_COPY_A, and AMPERE_DMA_COPY_B from
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// src/common/sdk/nvidia/inc/class/clb0b5sw.h.
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//
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// +marshal
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type NVB0B5_ALLOCATION_PARAMETERS struct {
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_ structs.HostLayout
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Version uint32
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EngineType uint32
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}
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@ -441,6 +547,7 @@ type NVB0B5_ALLOCATION_PARAMETERS struct {
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//
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// +marshal
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type NV_GR_ALLOCATION_PARAMETERS struct {
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_ structs.HostLayout
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Version uint32
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Flags uint32
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Size uint32
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@ -452,6 +559,7 @@ type NV_GR_ALLOCATION_PARAMETERS struct {
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//
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// +marshal
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type NV_HOPPER_USERMODE_A_PARAMS struct {
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_ structs.HostLayout
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Bar1Mapping uint8
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Priv uint8
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}
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@ -461,6 +569,7 @@ type NV_HOPPER_USERMODE_A_PARAMS struct {
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//
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// +marshal
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type NV9072_ALLOCATION_PARAMETERS struct {
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||||
_ structs.HostLayout
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LogicalHeadID uint32
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DisplayMask uint32
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Caps uint32
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@ -471,6 +580,7 @@ type NV9072_ALLOCATION_PARAMETERS struct {
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|||
//
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||||
// +marshal
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||||
type NV00DE_ALLOC_PARAMETERS struct {
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_ structs.HostLayout
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||||
Reserved uint32
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||||
}
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|
||||
|
|
@ -479,21 +589,76 @@ type NV00DE_ALLOC_PARAMETERS struct {
|
|||
//
|
||||
// +marshal
|
||||
type NV00DE_ALLOC_PARAMETERS_V545 struct {
|
||||
_ structs.HostLayout
|
||||
PolledDataMask uint64
|
||||
}
|
||||
|
||||
// +marshal
|
||||
type nv00f8Map struct {
|
||||
_ structs.HostLayout
|
||||
offset uint64
|
||||
hVidMem Handle
|
||||
flags uint32
|
||||
}
|
||||
|
||||
// From src/common/sdk/nvidia/inc/class/cl00e0.h:
|
||||
const (
|
||||
NV_MEM_EXPORT_UUID_LEN = 16
|
||||
NV_MEM_EXPORT_METADATA_LEN = 64
|
||||
)
|
||||
|
||||
// NV_EXPORT_MEM_PACKET is from
|
||||
// src/common/sdk/nvidia/inc/class/cl00e0.h
|
||||
//
|
||||
// +marshal
|
||||
type NV_EXPORT_MEM_PACKET struct {
|
||||
_ structs.HostLayout
|
||||
UUID [NV_MEM_EXPORT_UUID_LEN]uint8
|
||||
Opaque [16]uint8
|
||||
}
|
||||
|
||||
// NV00E0_ALLOCATION_PARAMETERS is the alloc params type for NV_MEMORY_EXPORT,
|
||||
// from src/common/sdk/nvidia/inc/class/cl00e0.h.
|
||||
//
|
||||
// +marshal
|
||||
type NV00E0_ALLOCATION_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
IMEXChannel uint32
|
||||
Packet NV_EXPORT_MEM_PACKET
|
||||
NumMaxHandles uint16
|
||||
Pad0 [2]byte
|
||||
Flags uint32
|
||||
Metadata [NV_MEM_EXPORT_METADATA_LEN]uint8
|
||||
DeviceInstanceMask uint32
|
||||
GIIDMasks [NV_MAX_DEVICES]uint32
|
||||
NumCurHandles uint16
|
||||
Pad1 [2]byte
|
||||
}
|
||||
|
||||
// NV00F1_ALLOCATION_PARAMETERS is the alloc params type for NV_IMEX_SESSION,
|
||||
// from src/common/sdk/nvidia/inc/class/cl00f1.h.
|
||||
//
|
||||
// +marshal
|
||||
type NV00F1_ALLOCATION_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
CapDescriptor uint64
|
||||
Flags uint32
|
||||
Pad0 [4]byte
|
||||
// Despite being P64-typed by the driver, pOsEvent is a file descriptor
|
||||
// whose numerical value is used by the driver. See
|
||||
// src/nvidia/src/kernel/compute/imex_session_api.c:imexsessionapiConstruct_IMPL()
|
||||
// => src/nvidia/arch/nvalloc/unix/src/os.c:osUserHandleToKernelPtr().
|
||||
POsEvent P64
|
||||
NodeID uint16
|
||||
Pad1 [6]byte
|
||||
}
|
||||
|
||||
// NV00F8_ALLOCATION_PARAMETERS is the alloc param type for NV_MEMORY_FABRIC,
|
||||
// from src/common/sdk/nvidia/inc/class/cl00f8.h.
|
||||
//
|
||||
// +marshal
|
||||
type NV00F8_ALLOCATION_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
Alignment uint64
|
||||
AllocSize uint64
|
||||
PageSize uint64
|
||||
|
|
@ -502,18 +667,32 @@ type NV00F8_ALLOCATION_PARAMETERS struct {
|
|||
Map nv00f8Map
|
||||
}
|
||||
|
||||
// From src/common/sdk/nvidia/inc/class/cl00e0.h
|
||||
const (
|
||||
NV_MEM_EXPORT_UUID_LEN = 16
|
||||
)
|
||||
|
||||
// NV_EXPORT_MEM_PACKET is from
|
||||
// src/common/sdk/nvidia/inc/class/cl00e0.h
|
||||
// NV00FB_ALLOCATION_PARAMETERS is the alloc param type for
|
||||
// NV_MEMORY_FABRIC_IMPORTED_REF, from
|
||||
// src/common/sdk/nvidia/inc/class/cl00fb.h.
|
||||
//
|
||||
// +marshal
|
||||
type NV_EXPORT_MEM_PACKET struct {
|
||||
UUID [NV_MEM_EXPORT_UUID_LEN]uint8
|
||||
Opaque [16]uint8
|
||||
type NV00FB_ALLOCATION_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
ExportUUID [NV_MEM_EXPORT_UUID_LEN]uint8
|
||||
Index uint16
|
||||
Pad0 [2]byte
|
||||
Flags uint32
|
||||
ID uint64
|
||||
}
|
||||
|
||||
// HasPOsEvent is a type constraint for allocation parameter structs containing
|
||||
// an optional pOsEvent field. Despite being P64-typed by the driver, pOsEvent
|
||||
// is a file descriptor whose numerical value is resolved by the driver. So it
|
||||
// must be translated from a sandbox FD to a host FD. See
|
||||
// src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c:_memMulticastFabricDescriptorEnqueueWait()
|
||||
// => src/nvidia/arch/nvalloc/unix/src/os.c:osUserHandleToKernelPtr().
|
||||
//
|
||||
// This is necessary because, as of this writing (Go 1.20), there is no way to
|
||||
// enable field access using a Go type constraint.
|
||||
type HasPOsEvent interface {
|
||||
GetPOsEvent() P64
|
||||
SetPOsEvent(P64)
|
||||
}
|
||||
|
||||
// NV00FD_ALLOCATION_PARAMETERS is the alloc param type for NV_MEMORY_MULTICAST_FABRIC
|
||||
|
|
@ -521,13 +700,25 @@ type NV_EXPORT_MEM_PACKET struct {
|
|||
//
|
||||
// +marshal
|
||||
type NV00FD_ALLOCATION_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
Alignment uint64
|
||||
AllocSize uint64
|
||||
PageSize uint32
|
||||
AllocFlags uint32
|
||||
NumGPUs uint32
|
||||
_ uint32
|
||||
POsEvent P64
|
||||
// POsEvent is an optional file descriptor; see HasPOsEvent.
|
||||
POsEvent P64
|
||||
}
|
||||
|
||||
// GetPOsEvent implements HasPOsEvent.GetPOsEvent.
|
||||
func (p *NV00FD_ALLOCATION_PARAMETERS) GetPOsEvent() P64 {
|
||||
return p.POsEvent
|
||||
}
|
||||
|
||||
// SetPOsEvent implements HasPOsEvent.SetPOsEvent.
|
||||
func (p *NV00FD_ALLOCATION_PARAMETERS) SetPOsEvent(posEvent P64) {
|
||||
p.POsEvent = posEvent
|
||||
}
|
||||
|
||||
// NV00FD_ALLOCATION_PARAMETERS_V545 is the updated version of
|
||||
|
|
@ -535,17 +726,47 @@ type NV00FD_ALLOCATION_PARAMETERS struct {
|
|||
//
|
||||
// +marshal
|
||||
type NV00FD_ALLOCATION_PARAMETERS_V545 struct {
|
||||
_ structs.HostLayout
|
||||
ExpPacket NV_EXPORT_MEM_PACKET
|
||||
Index uint16
|
||||
_ [6]byte
|
||||
NV00FD_ALLOCATION_PARAMETERS
|
||||
}
|
||||
|
||||
// NV00FD_ALLOCATION_PARAMETERS_V590 is the updated version of
|
||||
// NV00FD_ALLOCATION_PARAMETERS since 590.44.01.
|
||||
//
|
||||
// +marshal
|
||||
type NV00FD_ALLOCATION_PARAMETERS_V590 struct {
|
||||
_ structs.HostLayout
|
||||
ExpPacket NV_EXPORT_MEM_PACKET
|
||||
Index uint16
|
||||
_ [6]byte
|
||||
Alignment uint64
|
||||
AllocSize uint64
|
||||
PageSize uint64
|
||||
AllocFlags uint32
|
||||
NumGPUs uint32
|
||||
// POsEvent is an optional file descriptor; see HasPOsEvent.
|
||||
POsEvent P64
|
||||
}
|
||||
|
||||
// GetPOsEvent implements HasPOsEvent.GetPOsEvent.
|
||||
func (p *NV00FD_ALLOCATION_PARAMETERS_V590) GetPOsEvent() P64 {
|
||||
return p.POsEvent
|
||||
}
|
||||
|
||||
// SetPOsEvent implements HasPOsEvent.SetPOsEvent.
|
||||
func (p *NV00FD_ALLOCATION_PARAMETERS_V590) SetPOsEvent(posEvent P64) {
|
||||
p.POsEvent = posEvent
|
||||
}
|
||||
|
||||
// NV_MEMORY_MAPPER_ALLOCATION_PARAMS is the alloc param type for
|
||||
// NV_MEMORY_MAPPER, from src/common/sdk/nvidia/inc/class/cl00fe.h.
|
||||
//
|
||||
// +marshal
|
||||
type NV_MEMORY_MAPPER_ALLOCATION_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
unused uint8
|
||||
}
|
||||
|
||||
|
|
@ -554,6 +775,7 @@ type NV_MEMORY_MAPPER_ALLOCATION_PARAMS struct {
|
|||
//
|
||||
// +marshal
|
||||
type NV_MEMORY_MAPPER_ALLOCATION_PARAMS_V550 struct {
|
||||
_ structs.HostLayout
|
||||
HSemaphoreSurface Handle
|
||||
MaxQueueSize uint32
|
||||
}
|
||||
|
|
@ -563,6 +785,7 @@ type NV_MEMORY_MAPPER_ALLOCATION_PARAMS_V550 struct {
|
|||
//
|
||||
// +marshal
|
||||
type NV_MEMORY_MAPPER_ALLOCATION_PARAMS_V555 struct {
|
||||
_ structs.HostLayout
|
||||
NV_MEMORY_MAPPER_ALLOCATION_PARAMS_V550
|
||||
HNotificationMemory Handle
|
||||
_ uint32
|
||||
|
|
@ -574,6 +797,7 @@ type NV_MEMORY_MAPPER_ALLOCATION_PARAMS_V555 struct {
|
|||
//
|
||||
// +marshal
|
||||
type NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Handle Handle
|
||||
}
|
||||
|
||||
|
|
@ -582,9 +806,51 @@ type NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS struct {
|
|||
//
|
||||
// +marshal
|
||||
type NVA0BC_ALLOC_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
CodecType uint32
|
||||
HResolution uint32
|
||||
VResolution uint32
|
||||
Version uint32
|
||||
HMem Handle
|
||||
}
|
||||
|
||||
// NV_NVJPG_ALLOCATION_PARAMETERS is the alloc params type for
|
||||
// NVxxD1_VIDEO_NVJPG classes, from src/common/sdk/nvidia/inc/nvos.h.
|
||||
//
|
||||
// +marshal
|
||||
type NV_NVJPG_ALLOCATION_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
Size uint32
|
||||
ProhibitMultipleInstances uint32
|
||||
EngineInstance uint32
|
||||
}
|
||||
|
||||
// NV_OFA_ALLOCATION_PARAMETERS is the alloc params type for
|
||||
// NVxxFA_VIDEO_OFA classes, from src/common/sdk/nvidia/inc/nvos.h.
|
||||
//
|
||||
// +marshal
|
||||
type NV_OFA_ALLOCATION_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
Size uint32
|
||||
ProhibitMultipleInstances uint32
|
||||
}
|
||||
|
||||
// NV_OFA_ALLOCATION_PARAMETERS_V545 is the updated version of
|
||||
// NV_OFA_ALLOCATION_PARAMETERS since 545.23.06.
|
||||
//
|
||||
// +marshal
|
||||
type NV_OFA_ALLOCATION_PARAMETERS_V545 struct {
|
||||
_ structs.HostLayout
|
||||
NV_OFA_ALLOCATION_PARAMETERS
|
||||
EngineInstance uint32
|
||||
}
|
||||
|
||||
// NVB2CC_ALLOC_PARAMETERS is the alloc params type for MAXWELL_PROFILER_DEVICE,
|
||||
// from src/common/sdk/nvidia/inc/class/clb2cc.h.
|
||||
//
|
||||
// +marshal
|
||||
type NVB2CC_ALLOC_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HClientTarget Handle
|
||||
HContextTarget Handle
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,6 +14,10 @@
|
|||
|
||||
package nvgpu
|
||||
|
||||
import (
|
||||
"structs"
|
||||
)
|
||||
|
||||
// From src/nvidia/interface/deprecated/rmapi_deprecated.h:
|
||||
const (
|
||||
RM_GSS_LEGACY_MASK = 0x00008000
|
||||
|
|
@ -38,6 +42,7 @@ const (
|
|||
//
|
||||
// +marshal
|
||||
type NVXXXX_CTRL_XXX_INFO struct {
|
||||
_ structs.HostLayout
|
||||
Index uint32
|
||||
Data uint32
|
||||
}
|
||||
|
|
@ -75,11 +80,15 @@ const (
|
|||
NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS = 0x288
|
||||
NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID = 0x289
|
||||
NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID = 0x290
|
||||
|
||||
NV0000_CTRL_GPU_INVALID_ID = 0xffffffff
|
||||
NV0000_CTRL_GPU_MAX_PROBED_GPUS = NV_MAX_DEVICES
|
||||
NV0000_GPU_MAX_GID_LENGTH = 0x100
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h:
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h:
|
||||
const (
|
||||
NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS = 0x301
|
||||
NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE = 0xb02
|
||||
)
|
||||
|
||||
// NV0000_CTRL_GPU_GET_ID_INFO_PARAMS is the param type for NV0000_CTRL_CMD_GPU_GET_ID_INFO,
|
||||
|
|
@ -87,6 +96,7 @@ const (
|
|||
//
|
||||
// +marshal
|
||||
type NV0000_CTRL_GPU_GET_ID_INFO_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GpuID uint32
|
||||
GpuFlags uint32
|
||||
DeviceInstance uint32
|
||||
|
|
@ -98,6 +108,27 @@ type NV0000_CTRL_GPU_GET_ID_INFO_PARAMS struct {
|
|||
NumaID int32
|
||||
}
|
||||
|
||||
// +marshal
|
||||
type NV0000_CTRL_GPU_ATTACH_IDS_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GPUIDs [NV0000_CTRL_GPU_MAX_PROBED_GPUS]uint32
|
||||
FailedID uint32
|
||||
}
|
||||
|
||||
// +marshal
|
||||
type NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GPUID uint32
|
||||
Flags uint32
|
||||
GPUUUID [NV0000_GPU_MAX_GID_LENGTH]byte
|
||||
UUIDStrLen uint32
|
||||
}
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h:
|
||||
const (
|
||||
NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS = 0x301
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h:
|
||||
const (
|
||||
NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO = 0xa04
|
||||
|
|
@ -105,15 +136,16 @@ const (
|
|||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h:
|
||||
const (
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = 0x101
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO = 0x102
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = 0x127
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 = 0x12b
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = 0x136
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX = 0x13a
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_FEATURES = 0x1f0
|
||||
NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS = 32
|
||||
NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE = 9
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = 0x101
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO = 0x102
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = 0x127
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 = 0x12b
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = 0x136
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX = 0x13a
|
||||
NV0000_CTRL_CMD_SYSTEM_GET_FEATURES = 0x1f0
|
||||
NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE = 256
|
||||
NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS = 32
|
||||
NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE = 9
|
||||
)
|
||||
|
||||
// NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS is the param type for NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS,
|
||||
|
|
@ -121,6 +153,7 @@ const (
|
|||
//
|
||||
// +marshal
|
||||
type NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GpuIDs [NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]uint32
|
||||
GpuCount uint32
|
||||
P2PCaps uint32
|
||||
|
|
@ -136,6 +169,7 @@ type NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS struct {
|
|||
//
|
||||
// +marshal
|
||||
type NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_V550 struct {
|
||||
_ structs.HostLayout
|
||||
NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS
|
||||
BusEgmPeerIDs P64
|
||||
}
|
||||
|
|
@ -154,6 +188,7 @@ const (
|
|||
|
||||
// +marshal
|
||||
type NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
FD int32
|
||||
DeviceInstance uint32
|
||||
MaxObjects uint16
|
||||
|
|
@ -173,6 +208,7 @@ func (p *NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS) SetFrontendFD(fd int
|
|||
|
||||
// +marshal
|
||||
type NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_V545 struct {
|
||||
_ structs.HostLayout
|
||||
FD int32
|
||||
DeviceInstance uint32
|
||||
GpuInstanceID uint32
|
||||
|
|
@ -193,12 +229,14 @@ func (p *NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_V545) SetFrontendFD(f
|
|||
|
||||
// +marshal
|
||||
type NV0000_CTRL_OS_UNIX_EXPORT_OBJECT struct {
|
||||
_ structs.HostLayout
|
||||
Type uint32 // enum NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE
|
||||
Data [12]byte // union
|
||||
}
|
||||
|
||||
// +marshal
|
||||
type NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Object NV0000_CTRL_OS_UNIX_EXPORT_OBJECT
|
||||
FD int32
|
||||
Flags uint32
|
||||
|
|
@ -216,6 +254,7 @@ func (p *NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS) SetFrontendFD(fd int32)
|
|||
|
||||
// +marshal
|
||||
type NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
FD int32
|
||||
Object NV0000_CTRL_OS_UNIX_EXPORT_OBJECT
|
||||
}
|
||||
|
|
@ -232,6 +271,7 @@ func (p *NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS) SetFrontendFD(fd int3
|
|||
|
||||
// +marshal
|
||||
type NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
FD int32
|
||||
HDevice Handle
|
||||
MaxObjects uint16
|
||||
|
|
@ -254,6 +294,7 @@ func (p *NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS) SetFrontendFD(fd int32
|
|||
|
||||
// +marshal
|
||||
type NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
FD int32
|
||||
HParent Handle
|
||||
Objects [NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS]Handle
|
||||
|
|
@ -274,6 +315,7 @@ func (p *NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS) SetFrontendFD(fd int
|
|||
|
||||
// +marshal
|
||||
type NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
SizeOfStrings uint32
|
||||
Pad [4]byte
|
||||
PDriverVersionBuffer P64
|
||||
|
|
@ -310,6 +352,7 @@ const (
|
|||
|
||||
// +marshal
|
||||
type NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
NumChannels uint32
|
||||
Pad [4]byte
|
||||
PChannelHandleList P64
|
||||
|
|
@ -331,6 +374,7 @@ const (
|
|||
//
|
||||
// +marshal
|
||||
type RmapiParamNvU32List struct {
|
||||
_ structs.HostLayout
|
||||
NumElems uint32
|
||||
Pad [4]byte
|
||||
List P64
|
||||
|
|
@ -338,9 +382,10 @@ type RmapiParamNvU32List struct {
|
|||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h:
|
||||
const (
|
||||
NV0080_CTRL_CMD_GR_GET_CAPS = 0x801102
|
||||
NV0080_CTRL_CMD_GR_GET_INFO = 0x801104
|
||||
NV0080_CTRL_CMD_GR_GET_CAPS_V2 = 0x801109
|
||||
NV0080_CTRL_CMD_GR_GET_CAPS = 0x801102
|
||||
NV0080_CTRL_CMD_GR_GET_INFO = 0x801104
|
||||
NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE = 0x801108
|
||||
NV0080_CTRL_CMD_GR_GET_CAPS_V2 = 0x801109
|
||||
)
|
||||
|
||||
// NV0080_CTRL_GET_CAPS_PARAMS is used to represent the following:
|
||||
|
|
@ -348,9 +393,11 @@ const (
|
|||
// - NV0080_CTRL_GR_GET_CAPS_PARAMS
|
||||
// - NV0080_CTRL_FIFO_GET_CAPS_PARAMS
|
||||
// - NV0080_CTRL_MSENC_GET_CAPS_PARAMS
|
||||
// - NV0080_CTRL_NVENC_GET_CAPS_PARAMS
|
||||
//
|
||||
// +marshal
|
||||
type NV0080_CTRL_GET_CAPS_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
CapsTblSize uint32
|
||||
Pad [4]byte
|
||||
CapsTbl P64
|
||||
|
|
@ -358,6 +405,7 @@ type NV0080_CTRL_GET_CAPS_PARAMS struct {
|
|||
|
||||
// +marshal
|
||||
type NV0080_CTRL_GR_ROUTE_INFO struct {
|
||||
_ structs.HostLayout
|
||||
Flags uint32
|
||||
Pad [4]byte
|
||||
Route uint64
|
||||
|
|
@ -373,6 +421,7 @@ const (
|
|||
//
|
||||
// +marshal
|
||||
type NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Result uint32
|
||||
Checksum uint32
|
||||
}
|
||||
|
|
@ -386,6 +435,7 @@ type NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS struct {
|
|||
//
|
||||
// +marshal
|
||||
type NvxxxCtrlXxxGetInfoParams struct {
|
||||
_ structs.HostLayout
|
||||
InfoListSize uint32
|
||||
Pad [4]byte
|
||||
InfoList P64
|
||||
|
|
@ -442,21 +492,42 @@ const (
|
|||
NV00DE_CTRL_CMD_REQUEST_DATA_POLL = 0xde0001
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl00e0.h:
|
||||
const (
|
||||
NV00E0_CTRL_CMD_IMPORT_MEM = 0xe00102
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl00f1.h:
|
||||
const (
|
||||
NV00F1_CTRL_CMD_GET_FABRIC_EVENTS = 0xf10001
|
||||
NV00F1_CTRL_CMD_FINISH_MEM_UNIMPORT = 0xf10002
|
||||
NV00F1_CTRL_CMD_DISABLE_IMPORTERS = 0xf10003
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h:
|
||||
const (
|
||||
NV00F8_CTRL_CMD_DESCRIBE = 0xf80102
|
||||
NV00F8_CTRL_CMD_ATTACH_MEM = 0xf80103
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl00fb.h:
|
||||
const (
|
||||
NV00FB_CTRL_CMD_VALIDATE = 0xfb0101
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h:
|
||||
const (
|
||||
NV00FD_CTRL_CMD_GET_INFO = 0xfd0101
|
||||
NV00FD_CTRL_CMD_ATTACH_MEM = 0xfd0102
|
||||
NV00FD_CTRL_CMD_ATTACH_GPU = 0xfd0104
|
||||
NV00FD_CTRL_CMD_DETACH_MEM = 0xfd0105
|
||||
NV00FD_CTRL_CMD_GET_INFO = 0xfd0101
|
||||
NV00FD_CTRL_CMD_ATTACH_MEM = 0xfd0102
|
||||
NV00FD_CTRL_CMD_ATTACH_GPU = 0xfd0104
|
||||
NV00FD_CTRL_CMD_DETACH_MEM = 0xfd0105
|
||||
NV00FD_CTRL_CMD_ATTACH_REMOTE_GPU = 0xfd0106
|
||||
NV00FD_CTRL_CMD_SET_FAILURE = 0xfd0107
|
||||
)
|
||||
|
||||
// +marshal
|
||||
type NV00FD_CTRL_ATTACH_GPU_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
HSubDevice Handle
|
||||
Flags uint32
|
||||
DevDescriptor uint64
|
||||
|
|
@ -475,6 +546,10 @@ const (
|
|||
NV2080_CTRL_CMD_BUS_GET_INFO_V2 = 0x20801823
|
||||
NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS = 0x2080182a
|
||||
NV2080_CTRL_CMD_BUS_GET_C2C_INFO = 0x2080182b
|
||||
NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS = 0x20801813
|
||||
NV2080_CTRL_CMD_BUS_GET_PEX_UTIL_COUNTERS = 0x20801819
|
||||
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS = 0x20801829
|
||||
NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS = 0x20801830
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h:
|
||||
|
|
@ -489,17 +564,26 @@ const (
|
|||
NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION = 0x20800301
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h:
|
||||
const (
|
||||
NV2080_CTRL_CMD_ECC_GET_REPAIR_STATUS = 0x20803404
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h:
|
||||
const (
|
||||
NV2080_CTRL_CMD_FB_GET_INFO = 0x20801301
|
||||
NV2080_CTRL_CMD_FB_GET_INFO_V2 = 0x20801303
|
||||
NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO = 0x20801315
|
||||
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO = 0x20801320
|
||||
NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT = 0x20801352
|
||||
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT = 0x20801358
|
||||
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS = 0x20801359
|
||||
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_V575 = NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT - 1
|
||||
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_V575 = NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS - 1
|
||||
NV2080_CTRL_CMD_FB_GET_INFO = 0x20801301
|
||||
NV2080_CTRL_CMD_FB_GET_INFO_V2 = 0x20801303
|
||||
NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO = 0x20801315
|
||||
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO = 0x20801320
|
||||
NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT = 0x20801352
|
||||
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT = 0x20801358
|
||||
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS = 0x20801359
|
||||
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_V575 = NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT - 1
|
||||
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_V575 = NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS - 1
|
||||
NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES = 0x20801322
|
||||
NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE = 0x2080130e
|
||||
NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION = 0x20801355
|
||||
NV2080_CTRL_CMD_FB_GET_FS_INFO = 0x20801346
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h:
|
||||
|
|
@ -516,6 +600,7 @@ const (
|
|||
|
||||
// +marshal
|
||||
type NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
BDisable uint8
|
||||
Pad1 [3]byte
|
||||
NumChannels uint32
|
||||
|
|
@ -553,6 +638,12 @@ const (
|
|||
NV2080_CTRL_CMD_GPU_GET_PID_INFO = 0x2080018e
|
||||
NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG = 0x20800195
|
||||
NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO = 0x208001a3
|
||||
NV2080_CTRL_CMD_GPU_GET_NVENC_SW_SESSION_STATS = 0x2080016d
|
||||
NV2080_CTRL_CMD_GPU_GET_NVFBC_SW_SESSION_STATS = 0x2080017b
|
||||
NV2080_CTRL_CMD_GPU_GET_SKYLINE_INFO = 0x2080019f
|
||||
NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS = 0x208001a4
|
||||
NV2080_CTRL_CMD_GPU_GET_RECOVERY_ACTION = 0x208001b2
|
||||
NV2080_CTRL_CMD_GPU_EXEC_REG_OPS = 0x20800122
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h:
|
||||
|
|
@ -560,6 +651,7 @@ const (
|
|||
NV2080_CTRL_CMD_GR_GET_INFO = 0x20801201
|
||||
NV2080_CTRL_CMD_GR_GET_ZCULL_INFO = 0x20801206
|
||||
NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND = 0x20801208
|
||||
NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS = 0x2080120f
|
||||
NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE = 0x20801210
|
||||
NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE = 0x20801218
|
||||
NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER = 0x2080121b
|
||||
|
|
@ -581,6 +673,7 @@ const (
|
|||
|
||||
// +marshal
|
||||
type NV2080_CTRL_GR_GET_INFO_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
NvxxxCtrlXxxGetInfoParams
|
||||
GRRouteInfo NV0080_CTRL_GR_ROUTE_INFO
|
||||
}
|
||||
|
|
@ -600,6 +693,44 @@ func (p *NV2080_CTRL_GR_GET_INFO_PARAMS) CtrlInfoList() P64 {
|
|||
return p.InfoList
|
||||
}
|
||||
|
||||
// NV2080_CTRL_GPU_REG_OP is the type of an individual register operation,
|
||||
// from src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h.
|
||||
//
|
||||
// +marshal
|
||||
type NV2080_CTRL_GPU_REG_OP struct {
|
||||
_ structs.HostLayout
|
||||
RegOp uint8
|
||||
RegType uint8
|
||||
RegStatus uint8
|
||||
RegQuad uint8
|
||||
RegGroupMask uint32
|
||||
RegSubGroupMask uint32
|
||||
RegOffset uint32
|
||||
RegValueHi uint32
|
||||
RegValueLo uint32
|
||||
RegAndNMaskHi uint32
|
||||
RegAndNMaskLo uint32
|
||||
}
|
||||
|
||||
// CtrlGpuRegOpSize is sizeof(NV2080_CTRL_GPU_REG_OP).
|
||||
var CtrlGpuRegOpSize = uint32((*NV2080_CTRL_GPU_REG_OP)(nil).SizeBytes())
|
||||
|
||||
// NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS is the params type for
|
||||
// NV2080_CTRL_CMD_GPU_EXEC_REG_OPS, from
|
||||
// src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h.
|
||||
//
|
||||
// +marshal
|
||||
type NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
HClientTarget Handle
|
||||
HChannelTarget Handle
|
||||
BNonTransactional uint32
|
||||
Reserved00 [2]uint32
|
||||
RegOpCount uint32
|
||||
RegOps P64
|
||||
GRRouteInfo NV0080_CTRL_GR_ROUTE_INFO
|
||||
}
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h:
|
||||
const (
|
||||
NV2080_CTRL_CMD_MC_GET_ARCH_INFO = 0x20801701
|
||||
|
|
@ -608,8 +739,13 @@ const (
|
|||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h:
|
||||
const (
|
||||
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS = 0x20803001
|
||||
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS = 0x20803002
|
||||
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS = 0x20803001
|
||||
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS = 0x20803002
|
||||
NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO = 0x20803083
|
||||
NV2080_CTRL_CMD_NVLINK_LOCK_REMAP_TABLE_AND_MSE = 0x2080309d
|
||||
NV2080_CTRL_CMD_NVLINK_SETUP_NVLE_ENCRYPTION_KEY = 0x208030a0
|
||||
NV2080_CTRL_CMD_NVLINK_GET_REMAP_TABLE_INFO_V2 = 0x208030a1
|
||||
NV2080_CTRL_CMD_NVLINK_GET_UPDATE_NVLE_LIDS_V2 = 0x208030a2
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h:
|
||||
|
|
@ -651,6 +787,7 @@ const (
|
|||
|
||||
// +marshal
|
||||
type NV503C_CTRL_REGISTER_VA_SPACE_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
HVASpace Handle
|
||||
Pad [4]byte
|
||||
VASpaceToken uint64
|
||||
|
|
@ -685,6 +822,7 @@ const (
|
|||
const (
|
||||
NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE = 0x90960106
|
||||
NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY = 0x90960107
|
||||
NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR = 0x90960101
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h:
|
||||
|
|
@ -696,6 +834,7 @@ const (
|
|||
const (
|
||||
NVA06C_CTRL_CMD_GPFIFO_SCHEDULE = 0xa06c0101
|
||||
NVA06C_CTRL_CMD_SET_TIMESLICE = 0xa06c0103
|
||||
NVA06C_CTRL_CMD_GET_TIMESLICE = 0xa06c0104
|
||||
NVA06C_CTRL_CMD_PREEMPT = 0xa06c0105
|
||||
)
|
||||
|
||||
|
|
@ -705,6 +844,33 @@ const (
|
|||
NVA06F_CTRL_CMD_BIND = 0xa06f0104
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrl90cc.h:
|
||||
const (
|
||||
NV90CC_CTRL_CMD_POWER_REQUEST_FEATURES = 0x90cc0301
|
||||
NV90CC_CTRL_CMD_POWER_RELEASE_FEATURES = 0x90cc0302
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrlb0cc.h:
|
||||
const (
|
||||
NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY = 0xb0cc0101
|
||||
NVB0CC_CTRL_CMD_RELEASE_HWPM_LEGACY = 0xb0cc0102
|
||||
NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC = 0xb0cc0103
|
||||
NVB0CC_CTRL_CMD_RELEASE_PM_AREA_SMPC = 0xb0cc0104
|
||||
NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM = 0xb0cc0105
|
||||
NVB0CC_CTRL_CMD_FREE_PMA_STREAM = 0xb0cc0106
|
||||
NVB0CC_CTRL_CMD_BIND_PM_RESOURCES = 0xb0cc0107
|
||||
NVB0CC_CTRL_CMD_UNBIND_PM_RESOURCES = 0xb0cc0108
|
||||
NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT = 0xb0cc0109
|
||||
NVB0CC_CTRL_CMD_EXEC_REG_OPS = 0xb0cc010a
|
||||
NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER = 0xb0cc010b
|
||||
NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER = 0xb0cc010c
|
||||
NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS = 0xb0cc010d
|
||||
NVB0CC_CTRL_CMD_SET_HS_CREDITS = 0xb0cc010e
|
||||
NVB0CC_CTRL_CMD_RESERVE_CCU_PROF = 0xb0cc0119
|
||||
NVB0CC_CTRL_CMD_POWER_REQUEST_FEATURES = 0xb0cc0301
|
||||
NVB0CC_CTRL_CMD_POWER_RELEASE_FEATURES = 0xb0cc0302
|
||||
)
|
||||
|
||||
// From src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h:
|
||||
const (
|
||||
NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = 0xcb330101
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
package nvgpu
|
||||
|
||||
import (
|
||||
"structs"
|
||||
|
||||
"github.com/sagernet/gvisor/pkg/marshal"
|
||||
)
|
||||
|
||||
|
|
@ -26,15 +28,16 @@ const NV_IOCTL_MAGIC = uint32('F')
|
|||
// Note that these are only the IOC_NR part of the ioctl command.
|
||||
const (
|
||||
// From kernel-open/common/inc/nv-ioctl-numbers.h:
|
||||
NV_IOCTL_BASE = 200
|
||||
NV_ESC_CARD_INFO = NV_IOCTL_BASE + 0
|
||||
NV_ESC_REGISTER_FD = NV_IOCTL_BASE + 1
|
||||
NV_ESC_ALLOC_OS_EVENT = NV_IOCTL_BASE + 6
|
||||
NV_ESC_FREE_OS_EVENT = NV_IOCTL_BASE + 7
|
||||
NV_ESC_CHECK_VERSION_STR = NV_IOCTL_BASE + 10
|
||||
NV_ESC_ATTACH_GPUS_TO_FD = NV_IOCTL_BASE + 12
|
||||
NV_ESC_SYS_PARAMS = NV_IOCTL_BASE + 14
|
||||
NV_ESC_WAIT_OPEN_COMPLETE = NV_IOCTL_BASE + 18
|
||||
NV_IOCTL_BASE = 200
|
||||
NV_ESC_CARD_INFO = NV_IOCTL_BASE + 0
|
||||
NV_ESC_REGISTER_FD = NV_IOCTL_BASE + 1
|
||||
NV_ESC_ALLOC_OS_EVENT = NV_IOCTL_BASE + 6
|
||||
NV_ESC_FREE_OS_EVENT = NV_IOCTL_BASE + 7
|
||||
NV_ESC_CHECK_VERSION_STR = NV_IOCTL_BASE + 10
|
||||
NV_ESC_ATTACH_GPUS_TO_FD = NV_IOCTL_BASE + 12
|
||||
NV_ESC_SYS_PARAMS = NV_IOCTL_BASE + 14
|
||||
NV_ESC_EXPORT_TO_DMABUF_FD = NV_IOCTL_BASE + 17
|
||||
NV_ESC_WAIT_OPEN_COMPLETE = NV_IOCTL_BASE + 18
|
||||
|
||||
// From kernel-open/common/inc/nv-ioctl-numa.h:
|
||||
NV_ESC_NUMA_INFO = NV_IOCTL_BASE + 15
|
||||
|
|
@ -59,10 +62,46 @@ const (
|
|||
// Frontend ioctl parameter structs, from src/common/sdk/nvidia/inc/nvos.h or
|
||||
// kernel-open/common/inc/nv-ioctl.h.
|
||||
|
||||
// IoctlCardInfo is nv_ioctl_card_info_t. NV_ESC_CARD_INFO takes an array of
|
||||
// IoctlCardInfo as parameter.
|
||||
//
|
||||
// +marshal
|
||||
type IoctlCardInfo struct {
|
||||
_ structs.HostLayout
|
||||
Valid uint8
|
||||
Pad0 [3]byte
|
||||
PCIInfo PCIInfo
|
||||
GPUID uint32
|
||||
InterruptLine uint16
|
||||
Pad1 [2]byte
|
||||
RegAddress uint64
|
||||
RegSize uint64
|
||||
FBAddress uint64
|
||||
FBSize uint64
|
||||
MinorNumber uint32
|
||||
DevName [10]byte
|
||||
Pad2 [2]byte
|
||||
}
|
||||
|
||||
// PCIInfo is nv_pci_info_t.
|
||||
//
|
||||
// +marshal
|
||||
type PCIInfo struct {
|
||||
_ structs.HostLayout
|
||||
Domain uint32
|
||||
Bus uint8
|
||||
Slot uint8
|
||||
Function uint8
|
||||
Pad0 uint8
|
||||
VendorID uint16
|
||||
DeviceID uint16
|
||||
}
|
||||
|
||||
// IoctlRegisterFD is the parameter type for NV_ESC_REGISTER_FD.
|
||||
//
|
||||
// +marshal
|
||||
type IoctlRegisterFD struct {
|
||||
_ structs.HostLayout
|
||||
CtlFD int32
|
||||
}
|
||||
|
||||
|
|
@ -70,6 +109,7 @@ type IoctlRegisterFD struct {
|
|||
//
|
||||
// +marshal
|
||||
type IoctlAllocOSEvent struct {
|
||||
_ structs.HostLayout
|
||||
HClient Handle
|
||||
HDevice Handle
|
||||
FD uint32
|
||||
|
|
@ -100,6 +140,7 @@ func (p *IoctlAllocOSEvent) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type IoctlFreeOSEvent struct {
|
||||
_ structs.HostLayout
|
||||
HClient Handle
|
||||
HDevice Handle
|
||||
FD uint32
|
||||
|
|
@ -130,6 +171,7 @@ func (p *IoctlFreeOSEvent) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type RMAPIVersion struct {
|
||||
_ structs.HostLayout
|
||||
Cmd uint32
|
||||
Reply uint32
|
||||
VersionString [64]byte
|
||||
|
|
@ -139,6 +181,7 @@ type RMAPIVersion struct {
|
|||
//
|
||||
// +marshal
|
||||
type IoctlSysParams struct {
|
||||
_ structs.HostLayout
|
||||
MemblockSize uint64
|
||||
}
|
||||
|
||||
|
|
@ -146,6 +189,7 @@ type IoctlSysParams struct {
|
|||
//
|
||||
// +marshal
|
||||
type IoctlWaitOpenComplete struct {
|
||||
_ structs.HostLayout
|
||||
Rc int32
|
||||
AdapterStatus uint32
|
||||
}
|
||||
|
|
@ -160,10 +204,119 @@ func (p *IoctlWaitOpenComplete) SetStatus(status uint32) {
|
|||
p.AdapterStatus = status
|
||||
}
|
||||
|
||||
// NV_DMABUF_EXPORT_MAX_HANDLES is the fixed size of the handle/offset/size
|
||||
// arrays in nv_ioctl_export_to_dma_buf_fd_t.
|
||||
// From kernel-open/common/inc/nv-ioctl.h.
|
||||
const NV_DMABUF_EXPORT_MAX_HANDLES = 128
|
||||
|
||||
// IoctlExportToDMABufFD is nv_ioctl_export_to_dma_buf_fd_t, the parameter type
|
||||
// for NV_ESC_EXPORT_TO_DMABUF_FD (kernel-open/common/inc/nv-ioctl.h).
|
||||
//
|
||||
// +marshal
|
||||
type IoctlExportToDMABufFD struct {
|
||||
_ structs.HostLayout
|
||||
FD int32
|
||||
HClient Handle
|
||||
TotalObjects uint32
|
||||
NumObjects uint32
|
||||
Index uint32
|
||||
Pad0 uint32
|
||||
TotalSize uint64
|
||||
Handles [NV_DMABUF_EXPORT_MAX_HANDLES]Handle
|
||||
Offsets [NV_DMABUF_EXPORT_MAX_HANDLES]uint64
|
||||
Sizes [NV_DMABUF_EXPORT_MAX_HANDLES]uint64
|
||||
Status uint32
|
||||
Pad1 uint32
|
||||
}
|
||||
|
||||
// GetFrontendFD implements HasFrontendFD.GetFrontendFD.
|
||||
func (p *IoctlExportToDMABufFD) GetFrontendFD() int32 { return p.FD }
|
||||
|
||||
// SetFrontendFD implements HasFrontendFD.SetFrontendFD.
|
||||
func (p *IoctlExportToDMABufFD) SetFrontendFD(fd int32) { p.FD = fd }
|
||||
|
||||
// GetStatus implements HasStatus.GetStatus.
|
||||
func (p *IoctlExportToDMABufFD) GetStatus() uint32 { return p.Status }
|
||||
|
||||
// SetStatus implements HasStatus.SetStatus.
|
||||
func (p *IoctlExportToDMABufFD) SetStatus(status uint32) { p.Status = status }
|
||||
|
||||
// IoctlExportToDMABufFD_V570 is the updated version of
|
||||
// nv_ioctl_export_to_dma_buf_fd_t since 570.86.15.
|
||||
//
|
||||
// +marshal
|
||||
type IoctlExportToDMABufFD_V570 struct {
|
||||
_ structs.HostLayout
|
||||
FD int32
|
||||
HClient Handle
|
||||
TotalObjects uint32
|
||||
NumObjects uint32
|
||||
Index uint32
|
||||
Pad0 uint32
|
||||
TotalSize uint64
|
||||
MappingType uint8
|
||||
Pad1 [3]byte
|
||||
Handles [NV_DMABUF_EXPORT_MAX_HANDLES]Handle
|
||||
Pad2 uint32
|
||||
Offsets [NV_DMABUF_EXPORT_MAX_HANDLES]uint64
|
||||
Sizes [NV_DMABUF_EXPORT_MAX_HANDLES]uint64
|
||||
Status uint32
|
||||
Pad3 uint32
|
||||
}
|
||||
|
||||
// GetFrontendFD implements HasFrontendFD.GetFrontendFD.
|
||||
func (p *IoctlExportToDMABufFD_V570) GetFrontendFD() int32 { return p.FD }
|
||||
|
||||
// SetFrontendFD implements HasFrontendFD.SetFrontendFD.
|
||||
func (p *IoctlExportToDMABufFD_V570) SetFrontendFD(fd int32) { p.FD = fd }
|
||||
|
||||
// GetStatus implements HasStatus.GetStatus.
|
||||
func (p *IoctlExportToDMABufFD_V570) GetStatus() uint32 { return p.Status }
|
||||
|
||||
// SetStatus implements HasStatus.SetStatus.
|
||||
func (p *IoctlExportToDMABufFD_V570) SetStatus(status uint32) { p.Status = status }
|
||||
|
||||
// IoctlExportToDMABufFD_V580 is the updated version of
|
||||
// nv_ioctl_export_to_dma_buf_fd_t since 580.65.06.
|
||||
//
|
||||
// +marshal
|
||||
type IoctlExportToDMABufFD_V580 struct {
|
||||
_ structs.HostLayout
|
||||
FD int32
|
||||
HClient Handle
|
||||
TotalObjects uint32
|
||||
NumObjects uint32
|
||||
Index uint32
|
||||
Pad0 uint32
|
||||
TotalSize uint64
|
||||
MappingType uint8
|
||||
AllowMmap uint8
|
||||
Pad1 [2]byte
|
||||
Handles [NV_DMABUF_EXPORT_MAX_HANDLES]Handle
|
||||
Pad2 uint32
|
||||
Offsets [NV_DMABUF_EXPORT_MAX_HANDLES]uint64
|
||||
Sizes [NV_DMABUF_EXPORT_MAX_HANDLES]uint64
|
||||
Status uint32
|
||||
Pad3 uint32
|
||||
}
|
||||
|
||||
// GetFrontendFD implements HasFrontendFD.GetFrontendFD.
|
||||
func (p *IoctlExportToDMABufFD_V580) GetFrontendFD() int32 { return p.FD }
|
||||
|
||||
// SetFrontendFD implements HasFrontendFD.SetFrontendFD.
|
||||
func (p *IoctlExportToDMABufFD_V580) SetFrontendFD(fd int32) { p.FD = fd }
|
||||
|
||||
// GetStatus implements HasStatus.GetStatus.
|
||||
func (p *IoctlExportToDMABufFD_V580) GetStatus() uint32 { return p.Status }
|
||||
|
||||
// SetStatus implements HasStatus.SetStatus.
|
||||
func (p *IoctlExportToDMABufFD_V580) SetStatus(status uint32) { p.Status = status }
|
||||
|
||||
// IoctlNVOS02ParametersWithFD is the parameter type for NV_ESC_RM_ALLOC_MEMORY.
|
||||
//
|
||||
// +marshal
|
||||
type IoctlNVOS02ParametersWithFD struct {
|
||||
_ structs.HostLayout
|
||||
Params NVOS02_PARAMETERS
|
||||
FD int32
|
||||
Pad0 [4]byte
|
||||
|
|
@ -181,6 +334,7 @@ func (p *IoctlNVOS02ParametersWithFD) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type NVOS02_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HRoot Handle
|
||||
HObjectParent Handle
|
||||
HObjectNew Handle
|
||||
|
|
@ -208,6 +362,7 @@ const (
|
|||
//
|
||||
// +marshal
|
||||
type NVOS00_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HRoot Handle
|
||||
HObjectParent Handle
|
||||
HObjectOld Handle
|
||||
|
|
@ -252,6 +407,7 @@ func GetRmAllocParamObj(isNVOS64 bool) RmAllocParamType {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS21_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HRoot Handle
|
||||
HObjectParent Handle
|
||||
HObjectNew Handle
|
||||
|
|
@ -322,6 +478,7 @@ func (n *NVOS21_PARAMETERS) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS55_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HClient Handle
|
||||
HParent Handle
|
||||
HObject Handle
|
||||
|
|
@ -345,6 +502,7 @@ func (n *NVOS55_PARAMETERS) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS57_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HClient Handle
|
||||
HObject Handle
|
||||
SharePolicy RS_SHARE_POLICY
|
||||
|
|
@ -365,6 +523,7 @@ func (n *NVOS57_PARAMETERS) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS30_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
Client Handle
|
||||
Device Handle
|
||||
Channel Handle
|
||||
|
|
@ -394,6 +553,7 @@ func (n *NVOS30_PARAMETERS) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS32_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HRoot Handle
|
||||
HObjectParent Handle
|
||||
Function uint32
|
||||
|
|
@ -424,6 +584,7 @@ const (
|
|||
// NVOS32AllocSize is the type of NVOS32Parameters.Data for
|
||||
// NVOS32_FUNCTION_ALLOC_SIZE.
|
||||
type NVOS32AllocSize struct {
|
||||
_ structs.HostLayout
|
||||
Owner uint32
|
||||
HMemory Handle
|
||||
Type uint32
|
||||
|
|
@ -472,6 +633,7 @@ const (
|
|||
//
|
||||
// +marshal
|
||||
type IoctlNVOS33ParametersWithFD struct {
|
||||
_ structs.HostLayout
|
||||
Params NVOS33_PARAMETERS
|
||||
FD int32
|
||||
Pad0 [4]byte
|
||||
|
|
@ -489,6 +651,7 @@ func (p *IoctlNVOS33ParametersWithFD) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type NVOS33_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HClient Handle
|
||||
HDevice Handle
|
||||
HMemory Handle
|
||||
|
|
@ -516,6 +679,7 @@ const (
|
|||
//
|
||||
// +marshal
|
||||
type NVOS34_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HClient Handle
|
||||
HDevice Handle
|
||||
HMemory Handle
|
||||
|
|
@ -539,6 +703,7 @@ func (n *NVOS34_PARAMETERS) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS39_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HObjectParent Handle
|
||||
HSubDevice Handle
|
||||
HObjectNew Handle
|
||||
|
|
@ -567,6 +732,7 @@ func (n *NVOS39_PARAMETERS) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS46_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
Client Handle
|
||||
Device Handle
|
||||
Dma Handle
|
||||
|
|
@ -595,6 +761,7 @@ func (n *NVOS46_PARAMETERS) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS46_PARAMETERS_V580 struct {
|
||||
_ structs.HostLayout
|
||||
Client Handle
|
||||
Device Handle
|
||||
Dma Handle
|
||||
|
|
@ -624,6 +791,7 @@ func (n *NVOS46_PARAMETERS_V580) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS47_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
Client Handle
|
||||
Device Handle
|
||||
Dma Handle
|
||||
|
|
@ -650,6 +818,7 @@ func (n *NVOS47_PARAMETERS) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS47_PARAMETERS_V550 struct {
|
||||
_ structs.HostLayout
|
||||
Client Handle
|
||||
Device Handle
|
||||
Dma Handle
|
||||
|
|
@ -676,6 +845,7 @@ func (n *NVOS47_PARAMETERS_V550) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS54_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HClient Handle
|
||||
HObject Handle
|
||||
Cmd uint32
|
||||
|
|
@ -699,6 +869,7 @@ func (n *NVOS54_PARAMETERS) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type NVOS56_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HClient Handle
|
||||
HDevice Handle
|
||||
HMemory Handle
|
||||
|
|
@ -724,6 +895,7 @@ func (n *NVOS56_PARAMETERS) SetStatus(status uint32) {
|
|||
// +marshal
|
||||
// +stateify savable
|
||||
type NVOS64_PARAMETERS struct {
|
||||
_ structs.HostLayout
|
||||
HRoot Handle
|
||||
HObjectParent Handle
|
||||
HObjectNew Handle
|
||||
|
|
|
|||
|
|
@ -18,13 +18,21 @@ package nvgpu
|
|||
|
||||
import (
|
||||
"fmt"
|
||||
"structs"
|
||||
)
|
||||
|
||||
// Device numbers.
|
||||
const (
|
||||
NV_MAJOR_DEVICE_NUMBER = 195 // from kernel-open/common/inc/nv.h
|
||||
NV_CONTROL_DEVICE_MINOR = 255 // from kernel-open/common/inc/nv-linux.h
|
||||
NVIDIA_UVM_PRIMARY_MINOR_NUMBER = 0 // from kernel-open/nvidia-uvm/uvm_common.h
|
||||
// From kernel-open/common/inc/nv-chardev-numbers.h:
|
||||
NV_MAJOR_DEVICE_NUMBER = 195
|
||||
NV_MINOR_DEVICE_NUMBER_REGULAR_MAX = 247
|
||||
NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE = 255
|
||||
|
||||
// From kernel-open/nvidia-uvm/uvm_common.h:
|
||||
NVIDIA_UVM_PRIMARY_MINOR_NUMBER = 0
|
||||
|
||||
// From kernel-open/nvidia/nv-caps.c:
|
||||
NV_CAP_DRV_MINOR_COUNT = 8192
|
||||
)
|
||||
|
||||
// Handle is NvHandle, from src/common/sdk/nvidia/inc/nvtypes.h.
|
||||
|
|
@ -32,6 +40,7 @@ const (
|
|||
// +marshal
|
||||
// +stateify savable
|
||||
type Handle struct {
|
||||
_ structs.HostLayout
|
||||
Val uint32
|
||||
}
|
||||
|
||||
|
|
@ -63,6 +72,7 @@ const (
|
|||
// +marshal
|
||||
// +stateify savable
|
||||
type RS_ACCESS_MASK struct {
|
||||
_ structs.HostLayout
|
||||
Limbs [SDK_RS_ACCESS_MAX_LIMBS]uint32 // RsAccessLimb
|
||||
}
|
||||
|
||||
|
|
@ -73,6 +83,7 @@ const SDK_RS_ACCESS_MAX_LIMBS = 1
|
|||
//
|
||||
// +marshal
|
||||
type RS_SHARE_POLICY struct {
|
||||
_ structs.HostLayout
|
||||
Target uint32
|
||||
AccessMask RS_ACCESS_MASK
|
||||
Type uint16
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -14,6 +14,10 @@
|
|||
|
||||
package nvgpu
|
||||
|
||||
import (
|
||||
"structs"
|
||||
)
|
||||
|
||||
// UVM ioctl commands.
|
||||
const (
|
||||
// From kernel-open/nvidia-uvm/uvm_linux_ioctl.h:
|
||||
|
|
@ -37,7 +41,9 @@ const (
|
|||
UVM_PAGEABLE_MEM_ACCESS = 39
|
||||
UVM_SET_PREFERRED_LOCATION = 42
|
||||
UVM_UNSET_PREFERRED_LOCATION = 43
|
||||
UVM_ENABLE_READ_DUPLICATION = 44
|
||||
UVM_DISABLE_READ_DUPLICATION = 45
|
||||
UVM_SET_ACCESSED_BY = 46
|
||||
UVM_UNSET_ACCESSED_BY = 47
|
||||
UVM_MIGRATE = 51
|
||||
UVM_MIGRATE_RANGE_GROUP = 53
|
||||
|
|
@ -54,6 +60,7 @@ const (
|
|||
|
||||
// +marshal
|
||||
type UVM_INITIALIZE_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Flags uint64
|
||||
RMStatus uint32
|
||||
Pad0 [4]byte
|
||||
|
|
@ -76,6 +83,7 @@ const (
|
|||
|
||||
// +marshal
|
||||
type UVM_CREATE_RANGE_GROUP_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
RangeGroupID uint64
|
||||
RMStatus uint32
|
||||
Pad0 [4]byte
|
||||
|
|
@ -93,6 +101,7 @@ func (p *UVM_CREATE_RANGE_GROUP_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_DESTROY_RANGE_GROUP_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
RangeGroupID uint64
|
||||
RMStatus uint32
|
||||
Pad0 [4]byte
|
||||
|
|
@ -110,6 +119,7 @@ func (p *UVM_DESTROY_RANGE_GROUP_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_REGISTER_GPU_VASPACE_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GPUUUID NvUUID
|
||||
RMCtrlFD int32
|
||||
HClient Handle
|
||||
|
|
@ -139,6 +149,7 @@ func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_UNREGISTER_GPU_VASPACE_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GPUUUID NvUUID
|
||||
RMStatus uint32
|
||||
}
|
||||
|
|
@ -155,6 +166,7 @@ func (p *UVM_UNREGISTER_GPU_VASPACE_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_REGISTER_CHANNEL_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GPUUUID NvUUID
|
||||
RMCtrlFD int32
|
||||
HClient Handle
|
||||
|
|
@ -188,6 +200,7 @@ func (p *UVM_REGISTER_CHANNEL_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_UNREGISTER_CHANNEL_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GPUUUID NvUUID
|
||||
HClient Handle
|
||||
HChannel Handle
|
||||
|
|
@ -204,8 +217,30 @@ func (p *UVM_UNREGISTER_CHANNEL_PARAMS) SetStatus(status uint32) {
|
|||
p.RMStatus = status
|
||||
}
|
||||
|
||||
// UVM_UNREGISTER_CHANNEL_PARAMS_V590 is the updated version of
|
||||
// UVM_UNREGISTER_CHANNEL_PARAMS since 590.44.01.
|
||||
//
|
||||
// +marshal
|
||||
type UVM_UNREGISTER_CHANNEL_PARAMS_V590 struct {
|
||||
_ structs.HostLayout
|
||||
HClient Handle
|
||||
HChannel Handle
|
||||
RMStatus uint32
|
||||
}
|
||||
|
||||
// GetStatus implements HasStatus.GetStatus.
|
||||
func (p *UVM_UNREGISTER_CHANNEL_PARAMS_V590) GetStatus() uint32 {
|
||||
return p.RMStatus
|
||||
}
|
||||
|
||||
// SetStatus implements HasStatus.SetStatus.
|
||||
func (p *UVM_UNREGISTER_CHANNEL_PARAMS_V590) SetStatus(status uint32) {
|
||||
p.RMStatus = status
|
||||
}
|
||||
|
||||
// +marshal
|
||||
type UVM_ENABLE_PEER_ACCESS_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GPUUUIDA NvUUID
|
||||
GPUUUIDB NvUUID
|
||||
RMStatus uint32
|
||||
|
|
@ -223,6 +258,7 @@ func (p *UVM_ENABLE_PEER_ACCESS_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_DISABLE_PEER_ACCESS_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GPUUUIDA NvUUID
|
||||
GPUUUIDB NvUUID
|
||||
RMStatus uint32
|
||||
|
|
@ -240,6 +276,7 @@ func (p *UVM_DISABLE_PEER_ACCESS_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_SET_RANGE_GROUP_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
RangeGroupID uint64
|
||||
RequestedBase uint64
|
||||
Length uint64
|
||||
|
|
@ -259,6 +296,7 @@ func (p *UVM_SET_RANGE_GROUP_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_MAP_EXTERNAL_ALLOCATION_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
Length uint64
|
||||
Offset uint64
|
||||
|
|
@ -292,6 +330,7 @@ func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550 struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
Length uint64
|
||||
Offset uint64
|
||||
|
|
@ -325,6 +364,7 @@ func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS_V550) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_FREE_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
Length uint64
|
||||
RMStatus uint32
|
||||
|
|
@ -341,8 +381,30 @@ func (p *UVM_FREE_PARAMS) SetStatus(status uint32) {
|
|||
p.RMStatus = status
|
||||
}
|
||||
|
||||
// UVM_FREE_PARAMS_V590 is the updated version of
|
||||
// UVM_FREE_PARAMS since 590.44.01.
|
||||
//
|
||||
// +marshal
|
||||
type UVM_FREE_PARAMS_V590 struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
RMStatus uint32
|
||||
Pad0 [4]byte
|
||||
}
|
||||
|
||||
// GetStatus implements HasStatus.GetStatus.
|
||||
func (p *UVM_FREE_PARAMS_V590) GetStatus() uint32 {
|
||||
return p.RMStatus
|
||||
}
|
||||
|
||||
// SetStatus implements HasStatus.SetStatus.
|
||||
func (p *UVM_FREE_PARAMS_V590) SetStatus(status uint32) {
|
||||
p.RMStatus = status
|
||||
}
|
||||
|
||||
// +marshal
|
||||
type UVM_REGISTER_GPU_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GPUUUID NvUUID
|
||||
NumaEnabled uint8
|
||||
Pad [3]byte
|
||||
|
|
@ -375,6 +437,7 @@ func (p *UVM_REGISTER_GPU_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_UNREGISTER_GPU_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GPUUUID NvUUID
|
||||
RMStatus uint32
|
||||
}
|
||||
|
|
@ -391,6 +454,7 @@ func (p *UVM_UNREGISTER_GPU_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_PAGEABLE_MEM_ACCESS_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
PageableMemAccess uint8
|
||||
Pad [3]byte
|
||||
RMStatus uint32
|
||||
|
|
@ -408,6 +472,7 @@ func (p *UVM_PAGEABLE_MEM_ACCESS_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_SET_PREFERRED_LOCATION_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
RequestedBase uint64
|
||||
Length uint64
|
||||
PreferredLocation NvUUID
|
||||
|
|
@ -427,6 +492,7 @@ func (p *UVM_SET_PREFERRED_LOCATION_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_SET_PREFERRED_LOCATION_PARAMS_V550 struct {
|
||||
_ structs.HostLayout
|
||||
RequestedBase uint64
|
||||
Length uint64
|
||||
PreferredLocation NvUUID
|
||||
|
|
@ -446,6 +512,7 @@ func (p *UVM_SET_PREFERRED_LOCATION_PARAMS_V550) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_UNSET_PREFERRED_LOCATION_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
RequestedBase uint64
|
||||
Length uint64
|
||||
RMStatus uint32
|
||||
|
|
@ -462,8 +529,28 @@ func (p *UVM_UNSET_PREFERRED_LOCATION_PARAMS) SetStatus(status uint32) {
|
|||
p.RMStatus = status
|
||||
}
|
||||
|
||||
// +marshal
|
||||
type UVM_ENABLE_READ_DUPLICATION_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
RequestedBase uint64
|
||||
Length uint64
|
||||
RMStatus uint32
|
||||
Pad0 [4]byte
|
||||
}
|
||||
|
||||
// GetStatus implements HasStatus.GetStatus.
|
||||
func (p *UVM_ENABLE_READ_DUPLICATION_PARAMS) GetStatus() uint32 {
|
||||
return p.RMStatus
|
||||
}
|
||||
|
||||
// SetStatus implements HasStatus.SetStatus.
|
||||
func (p *UVM_ENABLE_READ_DUPLICATION_PARAMS) SetStatus(status uint32) {
|
||||
p.RMStatus = status
|
||||
}
|
||||
|
||||
// +marshal
|
||||
type UVM_DISABLE_READ_DUPLICATION_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
RequestedBase uint64
|
||||
Length uint64
|
||||
RMStatus uint32
|
||||
|
|
@ -480,8 +567,29 @@ func (p *UVM_DISABLE_READ_DUPLICATION_PARAMS) SetStatus(status uint32) {
|
|||
p.RMStatus = status
|
||||
}
|
||||
|
||||
// +marshal
|
||||
type UVM_SET_ACCESSED_BY_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
RequestedBase uint64
|
||||
Length uint64
|
||||
AccessedByUUID NvUUID
|
||||
RMStatus uint32
|
||||
Pad0 [4]byte
|
||||
}
|
||||
|
||||
// GetStatus implements HasStatus.GetStatus.
|
||||
func (p *UVM_SET_ACCESSED_BY_PARAMS) GetStatus() uint32 {
|
||||
return p.RMStatus
|
||||
}
|
||||
|
||||
// SetStatus implements HasStatus.SetStatus.
|
||||
func (p *UVM_SET_ACCESSED_BY_PARAMS) SetStatus(status uint32) {
|
||||
p.RMStatus = status
|
||||
}
|
||||
|
||||
// +marshal
|
||||
type UVM_UNSET_ACCESSED_BY_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
RequestedBase uint64
|
||||
Length uint64
|
||||
AccessedByUUID NvUUID
|
||||
|
|
@ -501,6 +609,7 @@ func (p *UVM_UNSET_ACCESSED_BY_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_MIGRATE_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
Length uint64
|
||||
DestinationUUID NvUUID
|
||||
|
|
@ -530,6 +639,7 @@ func (p *UVM_MIGRATE_PARAMS) SetStatus(status uint32) {
|
|||
//
|
||||
// +marshal
|
||||
type UVM_MIGRATE_PARAMS_V550 struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
Length uint64
|
||||
DestinationUUID NvUUID
|
||||
|
|
@ -556,6 +666,7 @@ func (p *UVM_MIGRATE_PARAMS_V550) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_MIGRATE_RANGE_GROUP_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
RangeGroupID uint64
|
||||
DestinationUUID NvUUID
|
||||
RMStatus uint32
|
||||
|
|
@ -574,6 +685,7 @@ func (p *UVM_MIGRATE_RANGE_GROUP_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Buffer uint64
|
||||
Size uint64
|
||||
TargetVA uint64
|
||||
|
|
@ -594,6 +706,7 @@ func (p *UVM_TOOLS_READ_PROCESS_MEMORY_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Buffer uint64
|
||||
Size uint64
|
||||
TargetVA uint64
|
||||
|
|
@ -614,6 +727,7 @@ func (p *UVM_TOOLS_WRITE_PROCESS_MEMORY_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
Length uint64
|
||||
GPUUUID NvUUID
|
||||
|
|
@ -633,6 +747,7 @@ func (p *UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_UNMAP_EXTERNAL_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
Length uint64
|
||||
GPUUUID NvUUID
|
||||
|
|
@ -652,6 +767,7 @@ func (p *UVM_UNMAP_EXTERNAL_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_ALLOC_SEMAPHORE_POOL_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
Length uint64
|
||||
PerGPUAttributes [UVM_MAX_GPUS]UvmGpuMappingAttributes
|
||||
|
|
@ -672,6 +788,7 @@ func (p *UVM_ALLOC_SEMAPHORE_POOL_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_ALLOC_SEMAPHORE_POOL_PARAMS_V550 struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
Length uint64
|
||||
PerGPUAttributes [UVM_MAX_GPUS_V2]UvmGpuMappingAttributes
|
||||
|
|
@ -692,6 +809,7 @@ func (p *UVM_ALLOC_SEMAPHORE_POOL_PARAMS_V550) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
GPUUUID NvUUID
|
||||
PageableMemAccess uint8
|
||||
Pad [3]byte
|
||||
|
|
@ -710,6 +828,7 @@ func (p *UVM_PAGEABLE_MEM_ACCESS_ON_GPU_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_VALIDATE_VA_RANGE_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
Length uint64
|
||||
RMStatus uint32
|
||||
|
|
@ -728,6 +847,7 @@ func (p *UVM_VALIDATE_VA_RANGE_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_CREATE_EXTERNAL_RANGE_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
Base uint64
|
||||
Length uint64
|
||||
RMStatus uint32
|
||||
|
|
@ -746,6 +866,7 @@ func (p *UVM_CREATE_EXTERNAL_RANGE_PARAMS) SetStatus(status uint32) {
|
|||
|
||||
// +marshal
|
||||
type UVM_MM_INITIALIZE_PARAMS struct {
|
||||
_ structs.HostLayout
|
||||
UvmFD int32
|
||||
RMStatus uint32
|
||||
}
|
||||
|
|
@ -769,6 +890,7 @@ const (
|
|||
|
||||
// +marshal
|
||||
type UvmGpuMappingAttributes struct {
|
||||
_ structs.HostLayout
|
||||
GPUUUID NvUUID
|
||||
GPUMappingType uint32
|
||||
GPUCachingType uint32
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue