2c4ae3b0a4
Содержимое пина, зафиксированного в go.mod sing-box-lx, одним коммитом без истории. Полная история SagerNet/gvisor — 1.45 ГБ и клонируется в каждой CI-джобе; наша дельта — одна вставка в одну функцию, история для неё не нужна. Module path github.com/sagernet/gvisor сохранён намеренно: на него опирается replace-директива суперпроекта. Патч поверх — отдельным коммитом, чтобы дельта читалась одним git show и переносилась на новый пин копированием. SPECS/TASKS/048-GVISOR_HANDSHAKE_NIL_CRASH
496 lines
14 KiB
Go
496 lines
14 KiB
Go
// Copyright 2019 The gVisor Authors.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//go:build amd64
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// +build amd64
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package cpuid
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import (
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"context"
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"fmt"
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"io"
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)
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// FeatureSet defines features in terms of CPUID leaves and bits.
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// The kernel also exposes the presence of features to userspace through
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// a set of flags(HWCAP/HWCAP2) bits, exposed in the auxiliary vector, which
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// are necessary to read for some features (e.g. FSGSBASE).
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//
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// Common references:
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//
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// Intel:
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// - Intel SDM Volume 2, Chapter 3.2 "CPUID" (more up-to-date)
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// - Intel Application Note 485 (more detailed)
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//
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// AMD:
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// - AMD64 APM Volume 3, Appendix 3 "Obtaining Processor Information ..."
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//
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// +stateify savable
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type FeatureSet struct {
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// Function is the underlying CPUID Function.
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//
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// This is exported to allow direct calls of the underlying CPUID
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// function, where required.
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Function `state:".(Static)"`
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// hwCap stores HWCAP1/2 exposed from the elf auxiliary vector.
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hwCap hwCap
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}
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// saveFunction saves the function as a static query.
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func (fs *FeatureSet) saveFunction() Static {
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if s, ok := fs.Function.(Static); ok {
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return s
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}
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return fs.ToStatic()
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}
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// loadFunction saves the function as a static query.
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func (fs *FeatureSet) loadFunction(_ context.Context, s Static) {
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fs.Function = s
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}
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// Helper to convert 3 regs into 12-byte vendor ID.
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//
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//go:nosplit
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func vendorIDFromRegs(bx, cx, dx uint32) (r [12]byte) {
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for i := uint(0); i < 4; i++ {
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b := byte(bx >> (i * 8))
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r[i] = b
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}
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for i := uint(0); i < 4; i++ {
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b := byte(dx >> (i * 8))
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r[4+i] = b
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}
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for i := uint(0); i < 4; i++ {
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b := byte(cx >> (i * 8))
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r[8+i] = b
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}
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return r
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}
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// Helper to merge a 12-byte vendor ID back to registers.
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//
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// Used by static_amd64.go.
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func regsFromVendorID(r [12]byte) (bx, cx, dx uint32) {
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bx |= uint32(r[0])
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bx |= uint32(r[1]) << 8
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bx |= uint32(r[2]) << 16
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bx |= uint32(r[3]) << 24
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cx |= uint32(r[4])
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cx |= uint32(r[5]) << 8
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cx |= uint32(r[6]) << 16
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cx |= uint32(r[7]) << 24
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dx |= uint32(r[8])
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dx |= uint32(r[9]) << 8
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dx |= uint32(r[10]) << 16
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dx |= uint32(r[10]) << 24
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return
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}
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// VendorID is the 12-char string returned in ebx:edx:ecx for eax=0.
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//
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//go:nosplit
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func (fs FeatureSet) VendorID() [12]byte {
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_, bx, cx, dx := fs.query(vendorID)
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return vendorIDFromRegs(bx, cx, dx)
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}
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// Helper to deconstruct signature dword.
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//
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//go:nosplit
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func signatureSplit(v uint32) (ef, em, pt, f, m, sid uint8) {
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sid = uint8(v & 0xf)
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m = uint8(v>>4) & 0xf
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f = uint8(v>>8) & 0xf
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pt = uint8(v>>12) & 0x3
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em = uint8(v>>16) & 0xf
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ef = uint8(v >> 20)
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return
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}
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// ExtendedFamily is part of the processor signature.
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//
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//go:nosplit
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func (fs FeatureSet) ExtendedFamily() uint8 {
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ax, _, _, _ := fs.query(featureInfo)
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ef, _, _, _, _, _ := signatureSplit(ax)
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return ef
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}
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// ExtendedModel is part of the processor signature.
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//
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//go:nosplit
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func (fs FeatureSet) ExtendedModel() uint8 {
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ax, _, _, _ := fs.query(featureInfo)
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_, em, _, _, _, _ := signatureSplit(ax)
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return em
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}
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// ProcessorType is part of the processor signature.
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//
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//go:nosplit
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func (fs FeatureSet) ProcessorType() uint8 {
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ax, _, _, _ := fs.query(featureInfo)
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_, _, pt, _, _, _ := signatureSplit(ax)
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return pt
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}
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// Family is part of the processor signature.
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//
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//go:nosplit
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func (fs FeatureSet) Family() uint8 {
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ax, _, _, _ := fs.query(featureInfo)
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_, _, _, f, _, _ := signatureSplit(ax)
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return f
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}
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// Model is part of the processor signature.
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//
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//go:nosplit
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func (fs FeatureSet) Model() uint8 {
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ax, _, _, _ := fs.query(featureInfo)
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_, _, _, _, m, _ := signatureSplit(ax)
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return m
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}
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// SteppingID is part of the processor signature.
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//
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//go:nosplit
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func (fs FeatureSet) SteppingID() uint8 {
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ax, _, _, _ := fs.query(featureInfo)
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_, _, _, _, _, sid := signatureSplit(ax)
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return sid
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}
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// VirtualAddressBits returns the number of bits available for virtual
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// addresses.
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//
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//go:nosplit
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func (fs FeatureSet) VirtualAddressBits() uint32 {
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ax, _, _, _ := fs.query(addressSizes)
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return (ax >> 8) & 0xff
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}
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// PhysicalAddressBits returns the number of bits available for physical
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// addresses.
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//
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//go:nosplit
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func (fs FeatureSet) PhysicalAddressBits() uint32 {
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ax, _, _, _ := fs.query(addressSizes)
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return ax & 0xff
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}
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// CacheType describes the type of a cache, as returned in eax[4:0] for eax=4.
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type CacheType uint8
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const (
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// cacheNull indicates that there are no more entries.
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cacheNull CacheType = iota
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// CacheData is a data cache.
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CacheData
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// CacheInstruction is an instruction cache.
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CacheInstruction
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// CacheUnified is a unified instruction and data cache.
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CacheUnified
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)
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// Cache describes the parameters of a single cache on the system.
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//
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// This is returned by the Caches method on FeatureSet.
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type Cache struct {
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// Level is the hierarchical level of this cache (L1, L2, etc).
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Level uint32
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// Type is the type of cache.
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Type CacheType
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// FullyAssociative indicates that entries may be placed in any block.
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FullyAssociative bool
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// Partitions is the number of physical partitions in the cache.
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Partitions uint32
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// Ways is the number of ways of associativity in the cache.
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Ways uint32
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// Sets is the number of sets in the cache.
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Sets uint32
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// InvalidateHierarchical indicates that WBINVD/INVD from threads
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// sharing this cache acts upon lower level caches for threads sharing
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// this cache.
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InvalidateHierarchical bool
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// Inclusive indicates that this cache is inclusive of lower cache
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// levels.
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Inclusive bool
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// DirectMapped indicates that this cache is directly mapped from
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// address, rather than using a hash function.
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DirectMapped bool
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}
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// Caches describes the caches on the CPU.
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//
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// Only supported on Intel; requires allocation.
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func (fs FeatureSet) Caches() (caches []Cache) {
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if !fs.Intel() {
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return
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}
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// Check against the cache line, which should be consistent.
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cacheLine := fs.CacheLine()
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for i := uint32(0); ; i++ {
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out := fs.Query(In{
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Eax: uint32(intelDeterministicCacheParams),
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Ecx: i,
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})
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t := CacheType(out.Eax & 0xf)
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if t == cacheNull {
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break
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}
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lineSize := (out.Ebx & 0xfff) + 1
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if lineSize != cacheLine {
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panic(fmt.Sprintf("Mismatched cache line size: %d vs %d", lineSize, cacheLine))
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}
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caches = append(caches, Cache{
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Type: t,
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Level: (out.Eax >> 5) & 0x7,
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FullyAssociative: ((out.Eax >> 9) & 1) == 1,
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Partitions: ((out.Ebx >> 12) & 0x3ff) + 1,
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Ways: ((out.Ebx >> 22) & 0x3ff) + 1,
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Sets: out.Ecx + 1,
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InvalidateHierarchical: (out.Edx & 1) == 0,
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Inclusive: ((out.Edx >> 1) & 1) == 1,
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DirectMapped: ((out.Edx >> 2) & 1) == 0,
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})
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}
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return
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}
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// CacheLine is the size of a cache line in bytes.
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//
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// All caches use the same line size. This is not enforced in the CPUID
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// encoding, but is true on all known x86 processors.
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//
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//go:nosplit
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func (fs FeatureSet) CacheLine() uint32 {
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_, bx, _, _ := fs.query(featureInfo)
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return 8 * (bx >> 8) & 0xff
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}
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// HasFeature tests whether or not a feature is in the given feature set.
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//
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// This function is safe to call from a nosplit context, as long as the
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// FeatureSet does not have any masked features.
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//
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//go:nosplit
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func (fs FeatureSet) HasFeature(feature Feature) bool {
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return feature.check(fs)
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}
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// WriteCPUInfoTo is to generate a section of one cpu in /proc/cpuinfo. This is
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// a minimal /proc/cpuinfo, it is missing some fields like "microcode" that are
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// not always printed in Linux. Several fields are simply made up.
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func (fs FeatureSet) WriteCPUInfoTo(cpu, numCPU uint, w io.Writer) {
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// Avoid many redundant calls here, since this can occasionally appear
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// in the hot path. Read all basic information up front, see above.
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ax, _, _, _ := fs.query(featureInfo)
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ef, em, _, f, m, _ := signatureSplit(ax)
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vendor := fs.VendorID()
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fmt.Fprintf(w, "processor\t: %d\n", cpu)
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fmt.Fprintf(w, "vendor_id\t: %s\n", string(vendor[:]))
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fmt.Fprintf(w, "cpu family\t: %d\n", ((ef<<4)&0xff)|f)
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fmt.Fprintf(w, "model\t\t: %d\n", ((em<<4)&0xff)|m)
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fmt.Fprintf(w, "model name\t: %s\n", "unknown") // Unknown for now.
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fmt.Fprintf(w, "stepping\t: %s\n", "unknown") // Unknown for now.
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fmt.Fprintf(w, "cpu MHz\t\t: %.3f\n", cpuFreqMHz)
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// Pretend the CPU has 8192 KB of cache. Note that real /proc/cpuinfo exposes total L3 cache
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// size on Intel and per-core L2 cache size on AMD (as of Linux 6.1.0), so the value of this
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// field is not really important in practice. Any value that is chosen here will be wrong
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// by an order of magnitude on a significant chunk of x86 machines.
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// 8192 KB is selected because it is a reasonable size that will be effectively usable on
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// lightly loaded machines - most machines have 1-4MB of L3 cache per core.
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fmt.Fprintf(w, "cache size\t: 8192 KB\n")
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fmt.Fprintf(w, "physical id\t: 0\n") // Pretend all CPUs are in the same socket.
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fmt.Fprintf(w, "siblings\t: %d\n", numCPU)
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fmt.Fprintf(w, "core id\t\t: %d\n", cpu)
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fmt.Fprintf(w, "cpu cores\t: %d\n", numCPU) // Pretend each CPU is a distinct core (rather than a hyperthread).
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fmt.Fprintf(w, "apicid\t\t: %d\n", cpu)
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fmt.Fprintf(w, "initial apicid\t: %d\n", cpu)
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fmt.Fprintf(w, "fpu\t\t: yes\n")
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fmt.Fprintf(w, "fpu_exception\t: yes\n")
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fmt.Fprintf(w, "cpuid level\t: %d\n", uint32(xSaveInfo)) // Same as ax in vendorID.
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fmt.Fprintf(w, "wp\t\t: yes\n")
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fmt.Fprintf(w, "flags\t\t: %s\n", fs.FlagString())
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fmt.Fprintf(w, "bogomips\t: %.02f\n", cpuFreqMHz) // It's bogus anyway.
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fmt.Fprintf(w, "clflush size\t: %d\n", fs.CacheLine())
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fmt.Fprintf(w, "cache_alignment\t: %d\n", fs.CacheLine())
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fmt.Fprintf(w, "address sizes\t: %d bits physical, %d bits virtual\n", 46, 48)
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fmt.Fprintf(w, "power management:\n") // This is always here, but can be blank.
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fmt.Fprintf(w, "\n") // The /proc/cpuinfo file ends with an extra newline.
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}
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var (
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authenticAMD = [12]byte{'A', 'u', 't', 'h', 'e', 'n', 't', 'i', 'c', 'A', 'M', 'D'}
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genuineIntel = [12]byte{'G', 'e', 'n', 'u', 'i', 'n', 'e', 'I', 'n', 't', 'e', 'l'}
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)
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// AMD returns true if fs describes an AMD CPU.
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//
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//go:nosplit
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func (fs FeatureSet) AMD() bool {
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return fs.VendorID() == authenticAMD
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}
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// Intel returns true if fs describes an Intel CPU.
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//
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//go:nosplit
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func (fs FeatureSet) Intel() bool {
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return fs.VendorID() == genuineIntel
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}
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// Leaf 0 of xsaveinfo function returns the size for currently
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// enabled xsave features in ebx, the maximum size if all valid
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// features are saved with xsave in ecx, and valid XCR0 bits in
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// edx:eax.
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//
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// If xSaveInfo isn't supported, cpuid will not fault but will
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// return bogus values.
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var (
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xsaveSize = native(In{Eax: uint32(xSaveInfo)}).Ebx
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maxXsaveSize = native(In{Eax: uint32(xSaveInfo)}).Ecx
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amxTileCfgSize = native(In{Eax: uint32(xSaveInfo), Ecx: 17}).Eax
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amxTileDataSize = native(In{Eax: uint32(xSaveInfo), Ecx: 18}).Eax
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)
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const (
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// XCR0AMXMask are the bits that enable xsave to operate on AMX TILECFG
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// and TILEDATA.
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//
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// Note: TILECFG and TILEDATA are always either both enabled or both
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// disabled.
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//
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// See Intel® 64 and IA-32 Architectures Software Developer’s Manual Vol.1
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// section 13.3 for details.
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XCR0AMXMask = uint64((1 << 17) | (1 << 18))
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)
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// ExtendedStateSize returns the number of bytes needed to save the "extended
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// state" for the enabled features and the boundary it must be aligned to.
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// Extended state includes floating point registers, and other cpu state that's
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// not associated with the normal task context.
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//
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// Note: the return value matches the size of signal FP state frames.
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// Look at check_xstate_in_sigframe() in the kernel sources for more details.
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//
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//go:nosplit
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func (fs FeatureSet) ExtendedStateSize() (size, align uint) {
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if fs.UseXsave() {
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return uint(xsaveSize), 64
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}
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// If we don't support xsave, we fall back to fxsave, which requires
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// 512 bytes aligned to 16 bytes.
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return 512, 16
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}
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// AMXExtendedStateSize returns the number of bytes within the "extended state"
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// area that is used for AMX.
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func (fs FeatureSet) AMXExtendedStateSize() uint {
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if fs.UseXsave() {
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xcr0 := xgetbv(0)
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if (xcr0 & XCR0AMXMask) != 0 {
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return uint(amxTileCfgSize + amxTileDataSize)
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}
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}
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return 0
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}
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// ValidXCR0Mask returns the valid bits in control register XCR0.
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//
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// Always exclude AMX bits, because we do not support it.
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// TODO(gvisor.dev/issues/9896): Implement AMX Support.
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//
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//go:nosplit
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func (fs FeatureSet) ValidXCR0Mask() uint64 {
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if !fs.HasFeature(X86FeatureXSAVE) {
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return 0
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}
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ax, _, _, dx := fs.query(xSaveInfo)
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return (uint64(dx)<<32 | uint64(ax)) &^ XCR0AMXMask
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}
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// UseXsave returns the choice of fp state saving instruction.
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//
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//go:nosplit
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func (fs FeatureSet) UseXsave() bool {
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return fs.HasFeature(X86FeatureXSAVE) && fs.HasFeature(X86FeatureOSXSAVE)
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}
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// UseXsaveopt returns true if 'fs' supports the "xsaveopt" instruction.
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//
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//go:nosplit
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func (fs FeatureSet) UseXsaveopt() bool {
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return fs.UseXsave() && fs.HasFeature(X86FeatureXSAVEOPT)
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}
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// UseXsavec returns true if 'fs' supports the "xsavec" instruction.
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//
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//go:nosplit
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func (fs FeatureSet) UseXsavec() bool {
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return fs.UseXsaveopt() && fs.HasFeature(X86FeatureXSAVEC)
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}
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// UseFSGSBASE returns true if 'fs' supports the (RD|WR)(FS|GS)BASE instructions.
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func (fs FeatureSet) UseFSGSBASE() bool {
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HWCAP2_FSGSBASE := uint64(1) << 1
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return fs.HasFeature(X86FeatureFSGSBase) && ((fs.hwCap.hwCap2 & HWCAP2_FSGSBASE) != 0)
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}
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// archCheckHostCompatible checks for compatibility.
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func (fs FeatureSet) archCheckHostCompatible(hfs FeatureSet) error {
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// The size of a cache line must match, as it is critical to correctly
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// utilizing CLFLUSH. Other cache properties are allowed to change, as
|
||
// they are not important to correctness.
|
||
fsCache := fs.CacheLine()
|
||
hostCache := hfs.CacheLine()
|
||
if fsCache != hostCache {
|
||
return &ErrIncompatible{
|
||
reason: fmt.Sprintf("CPU cache line size %d incompatible with host cache line size %d", fsCache, hostCache),
|
||
}
|
||
}
|
||
|
||
return nil
|
||
}
|
||
|
||
// AllowedHWCap1 returns the HWCAP1 bits that the guest is allowed to depend
|
||
// on.
|
||
func (fs FeatureSet) AllowedHWCap1() uint64 {
|
||
// HWCAPS are not supported on amd64.
|
||
return 0
|
||
}
|
||
|
||
// AllowedHWCap2 returns the HWCAP2 bits that the guest is allowed to depend
|
||
// on.
|
||
func (fs FeatureSet) AllowedHWCap2() uint64 {
|
||
// HWCAPS are not supported on amd64.
|
||
return 0
|
||
}
|