117243aa02
Обновление снапшота с v0.0.0-20250811.0 на пин, которого требует sing-box после мержа 235 коммитов (upstream d620bbbf2 "Update gvisor to 20260727.0"). Прежний снапшот был взят 2026-08-04 ровно с той версии, на которой тогда стоял апстрим; разрыв возник 2026-08-05 вместе с его бампом. За год апстрим-gvisor изменил ~14 000 строк в 292 файлах. Значимое для нас — сетевой стек: tcp/connect.go (PMTU-discovery + исправление начального RTT/RTO: раньше задержка ACK внутри стека завышала стартовый таймаут на несколько RTT), tcp/snd.go, tcp/rcv.go, stack/conntrack.go, stack/packet_buffer.go. Всего 30 файлов в TCP и 37 в stack. Баг SPEC 048 апстрим НЕ исправил — проверено по коду новой версии: handleConnecting по-прежнему проверяет состояние endpoint'а, но не ep.h, а performHandshake так же зануляет h и отпускает мьютекс до Close(). Поэтому guard перенесён (12 строк) вместе со своим тестом (45 строк). Red/green проверен на новой базе: без guard'а тест падает с той же nil-паникой, что в полевом крашдампе; с ним зелёный.
155 lines
3.8 KiB
Go
155 lines
3.8 KiB
Go
// Copyright 2023 The gVisor Authors.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// Package tpu defines constants used to interact with TPUs. The constants are
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// derived from those listed in https://github.com/tensorflow/tpu/blob/master/tools/driver/drivers/char/tpu_common
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package tpu
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const (
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// SizeOfTPUV4InterruptList is the total number of valid
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// (BAR Index, Register Offset) pairs.
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SizeOfTPUV4InterruptList = uint64(45)
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// NumberOfTPUV4PageTables is the number of gasket page tables used by the
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// TPU V4 driver.
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NumberOfTPUV4PageTables = uint64(1)
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// TPUV4DeviceID is the PCI device ID of TPU V4 hardware.
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TPUV4DeviceID = 0x005E
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// SizeOfTPUV4liteInterruptList is the total number of valid
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// (BAR Index, Register Offset) pairs.
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SizeOfTPUV4liteInterruptList = uint64(37)
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// NumberOfTPUV4litePageTables is the number of gasket page tables used by the
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// TPU V4 driver
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NumberOfTPUV4litePageTables = uint64(1)
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// TPUV4liteDeviceID is the PCI device ID of TPU V4lite hardware.
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TPUV4liteDeviceID = 0x0056
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// TPUV5eDeviceID is the PCI device ID of TPU V5e hardware.
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TPUV5eDeviceID = 0x0063
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// TPUV5pDeviceID is the PCI device ID of TPU V5p hardware.
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TPUV5pDeviceID = 0x0062
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// TPUV6eDeviceID is the PCI device ID of TPU V6e hardware.
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TPUV6eDeviceID = 0x006f
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// TPUV6ePFDeviceID is PCI device ID of TPU V6e hardware PF.
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TPUV6ePFDeviceID = 0x006e
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// TPU7xDeviceID is the PCI device ID of TPU 7x hardware.
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TPU7xDeviceID = 0x0075
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// TPU7xPFDeviceID is the PCI device ID of TPU 7x hardware PF.
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TPU7xPFDeviceID = 0x0076
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)
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// TPUV4InterruptsMap maps BAR indices to valid register offsets.
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var (
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TPUV4InterruptsMap = map[uint64]map[uint64]struct{}{
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2: {
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0x15b0008: {},
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0x15b0000: {},
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0x16b0008: {},
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0x16b0000: {},
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0x17b0008: {},
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0x17b0000: {},
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0x18b0008: {},
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0x18b0000: {},
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0x19b0020: {},
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0x19b0000: {},
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0x19b0008: {},
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0x19b0010: {},
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0x19b0018: {},
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0x1ab0020: {},
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0x1ab0000: {},
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0x1ab0008: {},
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0x1ab0010: {},
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0x1ab0018: {},
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0x4720000: {},
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0x1bb0000: {},
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0x1bb0008: {},
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0x1bb0010: {},
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0x1bb0018: {},
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0x90000: {},
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0xb0000: {},
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0xd0000: {},
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0xf0000: {},
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0x110000: {},
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0x130000: {},
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0x150000: {},
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0x170000: {},
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0x190000: {},
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0x1b0000: {},
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0x1d0000: {},
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0x1f0000: {},
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0x210000: {},
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0x230000: {},
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0x250000: {},
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0x270000: {},
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0x290000: {},
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0x2b0000: {},
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0x2d0000: {},
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0x2f0000: {},
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0x310000: {},
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0x4720018: {},
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},
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}
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// TPUV4liteInterruptsMap maps BAR indices to valid register offsets.
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TPUV4liteInterruptsMap = map[uint64]map[uint64]struct{}{
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2: {
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0x19b0020: {},
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0x19b0000: {},
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0x19b0008: {},
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0x19b0010: {},
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0x19b0018: {},
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0x1ab0020: {},
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0x1ab0000: {},
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0x1ab0008: {},
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0x1ab0010: {},
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0x1ab0018: {},
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0x4720000: {},
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0x1bb0000: {},
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0x1bb0008: {},
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0x1bb0010: {},
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0x1bb0018: {},
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0x90000: {},
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0xb0000: {},
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0xd0000: {},
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0xf0000: {},
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0x110000: {},
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0x130000: {},
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0x150000: {},
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0x170000: {},
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0x190000: {},
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0x1b0000: {},
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0x1d0000: {},
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0x1f0000: {},
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0x210000: {},
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0x230000: {},
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0x250000: {},
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0x270000: {},
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0x290000: {},
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0x2b0000: {},
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0x2d0000: {},
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0x2f0000: {},
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0x310000: {},
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0x4720018: {},
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},
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}
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)
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