snapshot: sagernet/gvisor v0.0.0-20260727.0-sing-box-mod.1 + SPEC 048 guard
Обновление снапшота с v0.0.0-20250811.0 на пин, которого требует sing-box после мержа 235 коммитов (upstream d620bbbf2 "Update gvisor to 20260727.0"). Прежний снапшот был взят 2026-08-04 ровно с той версии, на которой тогда стоял апстрим; разрыв возник 2026-08-05 вместе с его бампом. За год апстрим-gvisor изменил ~14 000 строк в 292 файлах. Значимое для нас — сетевой стек: tcp/connect.go (PMTU-discovery + исправление начального RTT/RTO: раньше задержка ACK внутри стека завышала стартовый таймаут на несколько RTT), tcp/snd.go, tcp/rcv.go, stack/conntrack.go, stack/packet_buffer.go. Всего 30 файлов в TCP и 37 в stack. Баг SPEC 048 апстрим НЕ исправил — проверено по коду новой версии: handleConnecting по-прежнему проверяет состояние endpoint'а, но не ep.h, а performHandshake так же зануляет h и отпускает мьютекс до Close(). Поэтому guard перенесён (12 строк) вместе со своим тестом (45 строк). Red/green проверен на новой базе: без guard'а тест падает с той же nil-паникой, что в полевом крашдампе; с ним зелёный.
This commit is contained in:
Leadaxe
parent
ffebe42860
commit
117243aa02
293 changed files with 16413 additions and 2842 deletions
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@ -233,9 +233,10 @@ func readHWCap(auxvFilepath string) (hwCap, error) {
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for i := 0; i < l; i++ {
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tag := binary.LittleEndian.Uint64(auxv[i*16:])
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val := binary.LittleEndian.Uint64(auxv[i*16+8:])
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if tag == _AT_HWCAP {
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switch tag {
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case _AT_HWCAP:
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c.hwCap1 = val
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} else if tag == _AT_HWCAP2 {
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case _AT_HWCAP2:
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c.hwCap2 = val
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}
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@ -249,7 +250,7 @@ func readHWCap(auxvFilepath string) (hwCap, error) {
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func initHWCap() {
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c, err := readHWCap("/proc/self/auxv")
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if err != nil {
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log.Warningf("cpuid HWCap not initialized: %w", err)
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log.Warningf("cpuid HWCap not initialized: %v", err)
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} else {
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hostFeatureSet.hwCap = c
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}
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@ -192,7 +192,24 @@ func (fs FeatureSet) VirtualAddressBits() uint32 {
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//go:nosplit
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func (fs FeatureSet) PhysicalAddressBits() uint32 {
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ax, _, _, _ := fs.query(addressSizes)
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return ax & 0xff
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physBits := ax & 0xff
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if !fs.AMD() {
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return physBits
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}
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maxExtended, _, _, _ := fs.query(extendedFunctionInfo)
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if maxExtended < uint32(amdMemoryEncryptionInfo) {
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return physBits
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}
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memEncAX, memEncBX, _, _ := fs.query(amdMemoryEncryptionInfo)
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if memEncAX&amdMemoryEncryptionFeatureMask == 0 {
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return physBits
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}
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// AMD memory encryption reduces usable physical address width by the
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// CPUID-reported amount. Match Linux's
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// arch/x86/kernel/cpu/amd.c:early_detect_mem_encrypt().
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return physBits - ((memEncBX >> amdPhysAddrReductionShift) & amdPhysAddrReductionMask)
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}
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// CacheType describes the type of a cache, as returned in eax[4:0] for eax=4.
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@ -382,15 +399,16 @@ var (
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)
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const (
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// XCR0AMXMask are the bits that enable xsave to operate on AMX TILECFG
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// and TILEDATA.
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//
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// Note: TILECFG and TILEDATA are always either both enabled or both
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// disabled.
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// XCR0AmxCfgMask is the bits that enable xsave to operate on
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// AMX TILECFG.
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//
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// See Intel® 64 and IA-32 Architectures Software Developer’s Manual Vol.1
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// section 13.3 for details.
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XCR0AMXMask = uint64((1 << 17) | (1 << 18))
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XCR0AmxCfgMask = uint64(1 << 17)
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// XCR0AmxDataMask is the bits that enable xsave to operate on
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// AMX TILEDATA.
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XCR0AmxDataMask = uint64(1 << 18)
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)
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// ExtendedStateSize returns the number of bytes needed to save the "extended
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@ -415,13 +433,15 @@ func (fs FeatureSet) ExtendedStateSize() (size, align uint) {
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// AMXExtendedStateSize returns the number of bytes within the "extended state"
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// area that is used for AMX.
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func (fs FeatureSet) AMXExtendedStateSize() uint {
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total := uint(0)
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if fs.UseXsave() {
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xcr0 := xgetbv(0)
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if (xcr0 & XCR0AMXMask) != 0 {
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return uint(amxTileCfgSize + amxTileDataSize)
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// TILECFG is not part of AMX extended state, only TILEDATA.
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if (xcr0 & XCR0AmxDataMask) != 0 {
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total += uint(amxTileDataSize)
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}
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}
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return 0
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return total
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}
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// ValidXCR0Mask returns the valid bits in control register XCR0.
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@ -435,7 +455,7 @@ func (fs FeatureSet) ValidXCR0Mask() uint64 {
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return 0
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}
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ax, _, _, dx := fs.query(xSaveInfo)
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return (uint64(dx)<<32 | uint64(ax)) &^ XCR0AMXMask
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return (uint64(dx)<<32 | uint64(ax)) &^ (XCR0AmxCfgMask | XCR0AmxDataMask)
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}
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// UseXsave returns the choice of fp state saving instruction.
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@ -27,8 +27,8 @@ func (fs *FeatureSet) beforeSave() {}
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// +checklocksignore
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func (fs *FeatureSet) StateSave(stateSinkObject state.Sink) {
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fs.beforeSave()
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var FunctionValue Static
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FunctionValue = fs.saveFunction()
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FunctionValue := fs.saveFunction()
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_ = (Static)(FunctionValue)
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stateSinkObject.SaveValue(0, FunctionValue)
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stateSinkObject.Save(1, &fs.hwCap)
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}
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@ -63,15 +63,25 @@ const xSaveInfoNumLeaves = 64 // Maximum number of xSaveInfo leaves.
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// The "extended" functions.
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const (
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extendedStart cpuidFunction = 0x80000000
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extendedFunctionInfo cpuidFunction = extendedStart + 0 // Returns highest available extended function in eax.
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extendedFeatures = extendedStart + 1 // Returns some extended feature bits in edx and ecx.
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processorBrandString2 = extendedStart + 2 // Processor Name String Identifier.
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processorBrandString3 = extendedStart + 3 // Processor Name String Identifier.
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processorBrandString4 = extendedStart + 4 // Processor Name String Identifier.
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l1CacheAndTLBInfo = extendedStart + 5 // Returns L2 cache information.
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l2CacheInfo = extendedStart + 6 // Returns L2 cache information.
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addressSizes = extendedStart + 8 // Physical and virtual address sizes.
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extendedStart cpuidFunction = 0x80000000
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extendedFunctionInfo cpuidFunction = extendedStart + 0 // Returns highest available extended function in eax.
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extendedFeatures = extendedStart + 1 // Returns some extended feature bits in edx and ecx.
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processorBrandString2 = extendedStart + 2 // Processor Name String Identifier.
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processorBrandString3 = extendedStart + 3 // Processor Name String Identifier.
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processorBrandString4 = extendedStart + 4 // Processor Name String Identifier.
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l1CacheAndTLBInfo = extendedStart + 5 // Returns L2 cache information.
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l2CacheInfo = extendedStart + 6 // Returns L2 cache information.
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addressSizes = extendedStart + 8 // Physical and virtual address sizes.
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amdMemoryEncryptionInfo = extendedStart + 31 // AMD memory encryption information.
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)
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// AMD-defined memory encryption feature bits and fields.
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const (
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amdSecureMemoryEncryption = 1 << 0
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amdSecureEncryptedVirtualization = 1 << 1
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amdMemoryEncryptionFeatureMask = amdSecureMemoryEncryption | amdSecureEncryptedVirtualization
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amdPhysAddrReductionShift = 6
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amdPhysAddrReductionMask = 0x3f
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)
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var allowedBasicFunctions = [...]bool{
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@ -84,14 +94,15 @@ var allowedBasicFunctions = [...]bool{
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}
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var allowedExtendedFunctions = [...]bool{
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extendedFunctionInfo - extendedStart: true,
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extendedFeatures - extendedStart: true,
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addressSizes - extendedStart: true,
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processorBrandString2 - extendedStart: true,
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processorBrandString3 - extendedStart: true,
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processorBrandString4 - extendedStart: true,
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l1CacheAndTLBInfo - extendedStart: true,
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l2CacheInfo - extendedStart: true,
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extendedFunctionInfo - extendedStart: true,
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extendedFeatures - extendedStart: true,
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addressSizes - extendedStart: true,
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processorBrandString2 - extendedStart: true,
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processorBrandString3 - extendedStart: true,
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processorBrandString4 - extendedStart: true,
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l1CacheAndTLBInfo - extendedStart: true,
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l2CacheInfo - extendedStart: true,
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amdMemoryEncryptionInfo - extendedStart: true,
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}
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// Function executes a CPUID function.
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@ -119,7 +130,7 @@ func (i *In) normalize() {
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switch cpuidFunction(i.Eax) {
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case vendorID, featureInfo, intelCacheDescriptors, extendedFunctionInfo, extendedFeatures:
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i.Ecx = 0 // Ignore.
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case processorBrandString2, processorBrandString3, processorBrandString4, l1CacheAndTLBInfo, l2CacheInfo:
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case processorBrandString2, processorBrandString3, processorBrandString4, l1CacheAndTLBInfo, l2CacheInfo, amdMemoryEncryptionInfo:
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i.Ecx = 0 // Ignore.
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case intelDeterministicCacheParams, extendedFeatureInfo:
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// Preserve i.Ecx.
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